Controller and control method for dynamic random access memory

Patent metadata

Field	Value
Publication number	US-9966129-B1
Application number	US-201715599859-A
Country	US
Kind code	B1
Filing date	May 19, 2017
Priority date	Feb 16, 2017
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

A schedule for refreshing a dynamic random access memory (DRAM). Access commands for a DRAM are queued in a command queue. First-rank bank-refresh time points and second-rank bank-refresh time points are alternately provided within a refresh inspection interval for the microcontroller to alternately refresh a first rank and a second rank of the DRAM bank-by-bank based on the content contained in the command queue.

First claim

What is claimed is:

1. A dynamic random access memory controller, comprising:
a command queue with access commands queued therein, wherein the access commands are queued in the command queue waiting to be transmitted to a dynamic random access memory; and
a microcontroller,
wherein:
the microcontroller refreshes a plurality of banks of a first rank of the dynamic random access memory bank-by-bank respectively from a plurality of first-rank bank-refresh time points within a refresh inspection interval based on status of the command queue;
the microcontroller refreshes a plurality of banks of a second rank of the dynamic random access memory bank-by-bank respectively from a plurality of second-rank bank-refresh time points within the refresh inspection interval based on the status of the command queue; and
the first-rank bank-refresh time points and the second-rank bank-refresh time points are arranged alternately.

2. The dynamic random access memory controller as claimed in claim 1 , wherein:
the first-rank bank-refresh time points are equally separated by a first time interval.

3. The dynamic random access memory controller as claimed in claim 1 , wherein:
the second-rank bank-refresh time points are equally separated by a second time interval.

4. The dynamic random access memory controller as claimed in claim 1 , wherein:
the first-rank bank-refresh time points include a first-initial-bank refresh time point corresponding to an initial bank of the plurality of banks of the first rank, and the first-initial-bank refresh time point is at a beginning of the refresh inspection interval.

5. The dynamic random access memory controller as claimed in claim 4 , wherein:
the first-rank bank-refresh time points include a first-final-bank refresh time point corresponding to a final bank of the plurality of banks of the first rank;
the first-final-bank refresh time point within a current refresh inspection interval is distant from a first-initial-bank refresh time point in a following refresh inspection interval by a first time interval; and
the first-rank bank-refresh time points are equally separated by the first time interval.

6. The dynamic random access memory controller as claimed in claim 4 , wherein:
the second-rank bank-refresh time points include a second-initial-bank refresh time point corresponding to an initial bank of the plurality of banks of the second rank.

7. The dynamic random access memory controller as claimed in claim 6 , wherein:
the first-rank bank-refresh time points include a first-second-bank refresh time point corresponding to the second bank of the plurality of banks of the first rank; and
the first-initial-bank refresh time point is distant from the second-initial-bank refresh time point by an identical time interval as that separating the second-initial-bank refresh time point and the first-second-bank refresh time point.

8. The dynamic random access memory controller as claimed in claim 1 , wherein:
the microcontroller further uses a first counter to count how many times the first rank is entirely refreshed;
the microcontroller decreases the first counter by 1 every time encountering a first-initial-bank refresh time point among the plurality of first-rank bank-refresh time points, the first-initial-bank refresh time point corresponding to an initial bank of the plurality of banks of the first rank; and
when the first counter is 0 and there are access commands corresponding to the first rank waiting in the command queue, the microcontroller refreshes the first rank bank-by-bank at the plurality of first-rank bank-refresh time points and thereby the banks contained in the first rank and not being refreshed currently are accessible.

9. The dynamic random access memory controller as claimed in claim 8 , wherein:
the microcontroller further uses a second counter to count how many times the second rank is entirely refreshed;
the microcontroller decreases the second counter by 1 every time encountering a second-initial-bank refresh time point among the plurality of second-rank bank-refresh time points, the second-initial-bank refresh time point corresponding to an initial bank of the plurality of banks of the second rank; and
when the second counter is 0 and there are access commands corresponding to the second rank waiting in the command queue, the microcontroller refreshes the second rank bank-by-bank respectively from the plurality of second-rank bank-refresh time points and thereby the banks contained in the second rank and not being refreshed currently are accessible.

10. The dynamic random access memory controller as claimed in claim 9 , wherein:
the microcontroller repeatedly performs a per-rank refresh operation on the first rank when the first counter has not reached a first upper limit and no access command corresponding to the first rank is waiting in the command queue; and
the microcontroller repeatedly performs a per-rank refresh operation on the second rank when the second counter has not reached a second upper limit and no access command corresponding to the second rank is waiting in the command queue.

11. A control method for dynamic random access memory, comprising:
providing a command queue with access commands queued therein, wherein the access commands are queued in the command queue waiting to be transmitted to a dynamic random access memory;
refreshing a plurality of banks of a first rank of the dynamic random access memory bank-by-bank respectively from a plurality of first-rank bank-refresh time points within a refresh inspection interval based on the status of the command queue; and
refreshing a plurality of banks of a second rank of the dynamic random access memory bank-by-bank respectively from a plurality of second-rank bank-refresh time points within the refresh inspection interval based on the status of the command queue,
wherein the first-rank bank-refresh time points and the second-rank bank-refresh time points are arranged alternately.

12. The control method for dynamic random access memory as claimed in claim 11 , wherein:
the first-rank bank-refresh time points are equally separated by a first time interval.

13. The control method for dynamic random access memory as claimed in claim 11 , wherein:
the second-rank bank-refresh time points are equally separated by a second time interval.

14. The control method for dynamic random access memory as claimed in claim 11 , wherein:
the first-rank bank-refresh time points include a first-initial-bank refresh time point corresponding to an initial bank of the plurality of banks of the first rank, and the first-initial-bank refresh time point is at the beginning of the refresh inspection interval.

15. The control method for dynamic random access memory as claimed in claim 14 , wherein:
the second-rank bank-refresh time points include a second-initial-bank refresh time point corresponding to an initial bank of the plurality of banks of the second rank.

16. The control method for dynamic random access memory as claimed in claim 15 , wherein:
the first-rank bank-refresh time points include a first-second-bank refresh time point corresponding to the second bank of the plurality of banks of the first rank; and
the first-initial-bank refresh time point is distant from the second-initial-bank refresh time point by an identical time interval as that separating the second-initial-bank refresh time point and the first-second-bank refresh time point.

17. The control method for dynamic random access memory as claimed in claim 14 , wherein:
the first-

Assignees

• Via Alliance Semiconductor Co Ltd

Inventors

• Chen Chen
• Shen Peng

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C11/40615

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title