Systems and methods for proactively refreshing nonvolatile memory

Patent metadata

Field	Value
Publication number	US-9384089-B2
Application number	US-201314144957-A
Country	US
Kind code	B2
Filing date	Dec 31, 2013
Priority date	Jan 18, 2012
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

System and methods for proactively refreshing portions of a nonvolatile memory including a memory system that proactively refreshes a portion of nonvolatile memory based on data associated with the portion. The data may include the time elapsed since the portion was last refreshed, the number of times the portion has been cycled, and the average operating temperature of the nonvolatile memory. A portion of nonvolatile memory, when meeting certain criteria determined from the data, may be proactively refreshed during a downtime when the nonvolatile memory is not otherwise being accessed.

First claim

What is claimed is:

1. A system for proactively refreshing portions of a nonvolatile memory, comprising:
a nonvolatile memory comprising a plurality of portions;
a controller communicatively coupled to the nonvolatile memory, wherein portions of the nonvolatile memory are proactively refreshed based at least on an expected bit error rate calculated using data stored on the controller, wherein the data stored on the controller comprises:
a time elapsed since the portion of nonvolatile memory was last programmed, wherein the time elapsed is determined with reference to a real-time clock resident on a host device;
a number of times that the portion has been cycled; and
an average operating temperature of the nonvolatile memory; and

wherein the controller is operative to prioritize which portions of the nonvolatile memory are proactively refreshed.

2. The system of claim 1 , wherein each portion of the plurality of portions of the nonvolatile memory is a block comprising a plurality of pages.

3. The system of claim 1 , wherein each portion of the plurality of portions of the nonvolatile memory is an individual page.

4. The system of claim 1 , wherein the data stored on the host controller is transferred to the nonvolatile memory when the controller is shutdown.

5. The system of claim 1 , wherein the nonvolatile memory comprises NAND flash memory.

6. A method for proactively refreshing a portion of a nonvolatile memory, comprising:
determining whether a block of nonvolatile memory has an expected error rate higher than a predetermined refresh threshold;
refreshing the block of the nonvolatile memory when it is determined that the block has an expected error rate higher than a predetermined refresh threshold, wherein the expected error rate is calculated based on time elapsed since the block was last programmed, a number of times the block has been cycled, and an average operating temperature of the nonvolatile memory; and
prioritizing which portions of the nonvolatile memory are proactively refreshed.

7. The method of claim 6 , wherein refreshing the portion of nonvolatile memory comprises copying the contents of the portion from a first physical location of the nonvolatile memory to a second physical location of the nonvolatile memory.

8. The method of claim 7 , further comprising updating a database stored on a host device.

9. The method of claim 8 , wherein updating the database comprises:
tagging the portion of nonvolatile memory at the first physical location as invalid;
incrementing a number of cycles associated with the portion of nonvolatile memory at the second physical location; and
resetting a time elapsed field associated with the portion of nonvolatile memory at the second physical location.

10. The method of claim 8 , further comprising transferring the database stored on the host device to the nonvolatile memory when the controller is shutdown.

11. The method of claim 6 , wherein determining whether a block of nonvolatile memory has an expected error rate higher than a predetermined refresh threshold is independent of any error code correction parameter associated with that block.

Assignees

• Apple Inc

Inventors

• Fai Anthony

Classifications

• G06F11/106

  Correcting systematically all correctable errors, i.e. scrubbing · CPC title

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F11/076

  by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title

• G11C11/406 Primary

  Management or control of the refreshing or charge-regeneration cycles · CPC title