Semiconductor memory device for deconcentrating refresh commands and system including the same

Patent metadata

Field	Value
Publication number	US-9685219-B2
Application number	US-201615149751-A
Country	US
Kind code	B2
Filing date	May 9, 2016
Priority date	May 13, 2015
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

A memory device includes a buffer memory configured to receive commands from a memory controller via first to N th channels, wherein N denotes an integer which is equal to or greater than ‘2’; and first to N th core memories each connected to the buffer memory via one of the first to N th channels. The buffer memory may deconcentrate refresh commands corresponding to the first to N th core memories, based on a number of commands input during a specific time.

First claim

What is claimed is:

1. A memory device comprising:
a buffer memory configured to receive commands from a memory controller via first to N th channels, wherein N denotes an integer which is equal to or greater than two; and
first to N th core memories each connected to the buffer memory via one of the first to N th channels,
wherein the buffer memory deconcentrates refresh commands corresponding to the first to N th core memories that are input to the buffer memory via the first to Nth channels by skipping or delaying transmission of a refresh command among the refresh commands to one of the core memories based on a number of commands input during a specific period,
wherein the buffer memory comprises a refresh control determining circuit configured to count a number of commands received via the first to N th channels during the specific period to generate a count value, and compare the count value with a preset threshold to determine whether the refresh commands are to be deconcentrated.

2. The memory device of claim 1 , wherein the refresh control determining circuit counts only refresh commands among the commands received via the first to N th channels to generate the count value, and outputs a refresh control signal based on a result of the compare.

3. The memory device of claim 2 , wherein the buffer memory comprises:
command decoders corresponding to the first to N th channels, and configured to decode the commands received via the first to N th channels and output command selection signals according to whether the decoded commands are refresh commands or not;
refresh control circuits corresponding to the first to N th channels, and configured to selectively delay or skip the refresh commands according to the refresh control signal; and
selectors corresponding to the first to N th channels, and configured to each select one of commands output from the refresh control circuits and bypassed commands and to respectively transmit the selected commands to the first to N th core memories, according to the command selection signals,
wherein the bypassed commands are normal commands other than the refresh commands that do not pass through the refresh control circuits.

4. The memory device of claim 2 , wherein the refresh control determining circuit comprises:
a command counter configured to count a number of the refresh commands input during the specific period and output the count value; and
a comparator configured to enable the refresh control signal when the count value is equal to or greater than the preset threshold.

5. The memory device of claim 1 , wherein the refresh control determining circuit comprises:
a refresh detector configured to determine whether at least one of the refresh commands is input via the first to N th channels during the specific period, and output a latch output signal; and
a voting block configured to be enabled to determine whether the number of the refresh commands is equal to or greater than the preset threshold and output a refresh delay control signal, according to the latch output signal.

6. The memory device of claim 5 , wherein the refresh detector comprises an oscillator configured to generate an oscillator output signal having a predetermined cycle, in response to the latch output signal,
wherein the latch output signal is reset based on the oscillator output signal.

7. The memory device of claim 5 , Wherein the buffer memory comprises:
command decoders corresponding to the first to N th channels, and configured to decode the commands received via the first to N th channels and output command selection signals according to whether the decoded commands are refresh commands or not;
refresh delay circuits corresponding to the first to N th channels, and configured to selectively delay the refresh commands according to the refresh control signal; and
selectors corresponding to the first to N th channels, and configured to each select one of commands output from the refresh delay modules and bypassed commands and respectively transmit the selected commands to the first to N th core memories, according to the command selection signal.

8. The memory device of claim 7 , wherein the command decoders output a command selection signal having a first logic level when the decoded commands are the refresh commands, and output a command selection signal having a second logic level when the decoded commands are not the refresh commands.

9. The memory device of claim 5 , wherein the refresh delay circuits output the refresh commands without delaying the refresh commands when the refresh delay control signal has a first logic level, and delay the refresh commands using at least one delay circuit and output the delayed refresh commands when the refresh delay control signal has a second logic level.

10. The memory device of claim 5 , wherein at least two among the refresh delay circuits, delay signals input thereto for different delay periods.

11. The memory device of claim 1 , wherein a memory comprising the buffer memory and the core memories has a three-dimensional (3D) stack structure.

12. A memory system comprising:
a memory controller;
first to N th core memories configured to communicate with the memory controller via first to N th independent channels, wherein N denotes an integer which is equal to or greater than two; and
a buffer memory configured to transmit commands and data to be exchanged between the memory controller and the first to N th core memories,
wherein the buffer memory deconcentrates refresh commands corresponding to the first to N th core memories that are input to the buffer memory via the first to Nth channels by skipping transmission of a refresh command among the refresh commands to one of the core memories based on a number of commands input during a specific period.

13. The memory system of claim 12 , wherein the buffer memory comprises a refresh control determining circuit configured to count a number of all commands received via the first to N th channels during a specific period to generate a count value, and compare the count value with a preset threshold to determine whether the refresh commands are to be deconcentrated.

14. The memory system of claim 12 , wherein the buffer memory counts a number of the refresh commands received via the first to N th channel during a specific period to generate a count value, and compares the count value with a preset threshold to determine whether the refresh commands are to be deconcentrated.

15. The memory system of claim 14 , wherein the buffer memory comprises:
command decoders corresponding to the first to N th channels, and configured to decode the commands received via the first to N th channels and output command selection signals according to whether the decoded commands are refresh commands or not;
refresh control circuits corresponding to the first to N th channels, and configured to selectively skip the refresh commands according to a refresh control signal; and
selectors corresponding to the first to N th channels, and configured to each select one of commands output from the refresh control circuits and bypassed commands and respectively transmit the selected commands to the first to N th core memories, according to the command selection signal,
wherein the bypassed commands are normal commands other than the refresh commands that do not pass through the refresh control circuits.

16. The memory system of claim 14 , wherein the refresh control determining circuit comprises:
a command counter configured to count the number of the refresh comm

Assignees

• Samsung Electronics Co Ltd

Inventors

• Shin Dong Hak

Classifications

• G11C11/40611

  External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh · CPC title

• G11C11/40607 Primary

  Refresh operations in memory devices with an internal cache or data buffer · CPC title

• G11C11/406 Primary

  Management or control of the refreshing or charge-regeneration cycles · CPC title

• G11C11/40618

  Refresh operations over multiple banks or interleaving · CPC title

• G11C7/106

  Data output latches · CPC title