Integrated assemblies having shield lines between digit lines, and methods of forming integrated assemblies

Patent metadata

Field	Value
Publication number	US-11069687-B2
Application number	US-202016809924-A
Country	US
Kind code	B2
Filing date	Mar 5, 2020
Priority date	Mar 6, 2019
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

Some embodiments include an integrated assembly having digit lines which extend along a first direction, and which are spaced from one another by intervening regions. Each of the intervening regions has a first width along a cross-section. Pillars extend upwardly from the digit lines; and the pillars include transistor channel regions extending vertically between upper and lower source/drain regions. Storage elements are coupled with the upper source/drain regions. Wordlines extend along a second direction which crosses the first direction. The wordlines include gate regions adjacent the channel regions. Shield lines are within the intervening regions and extend along the first direction. The shield lines may be coupled with at least one reference voltage node. Some embodiments include methods of forming integrated assemblies.

First claim

We claim:

1. An integrated assembly, comprising:
digit lines extending along a first direction; the digit lines being spaced from one another by intervening regions; each of the digit lines having a first width along a cross-section orthogonal to the first direction; each of the intervening regions also having the first width along the cross-section; each of the digit lines having a top surface at a first height;
vertically-extending pillars over the digit lines; each of the vertically-extending pillars comprising a transistor channel region and an upper source/drain region; lower source/drain regions being under the channel regions and being coupled with the digit lines; the transistor channel regions extending vertically between the lower source/drain regions and the upper source/drain regions; each of the vertically-extending pillars having the first width along the cross-section; the intervening regions extending upwardly to between the vertically-extending pillars and comprising the first width from top surfaces of the upper source/drain regions to bottom surfaces of the digit lines;
storage elements coupled with the upper source/drain regions;
wordlines extending along a second direction which crosses the first direction; the wordlines including gate regions adjacent the channel regions; and
shield lines within the intervening regions and extending along the first direction; each of the shield lines having a top surface at a second height which is greater than or equal to the first height.

2. The integrated assembly of claim 1 wherein the storage elements are capacitors.

3. The integrated assembly of claim 1 wherein the vertically-extending pillars comprise one or more semiconductor materials.

4. The integrated assembly of claim 1 wherein the storage elements are comprised by memory cells of a memory array; wherein the digit lines extend along columns of the memory array and the wordlines extend along rows of the memory array; wherein one of columns is an edge column; the edge column having one of the intervening regions extending along one side, and having an edge region extending along a second side in opposing relation to said one side; the shield lines within the intervening regions being first shield lines and being configured as vertically-extending plates; one of the shield lines being within the edge region and being a second shield line; the second shield line being configured different than the first shield lines and comprising an elbow region connecting a vertically-extending region to a horizontally-extending region.

5. The integrated assembly of claim 1 wherein each of the shield lines has a second width along the cross-section; and wherein the second width is less than or equal to about one-half of the first width.

6. The integrated assembly of claim 5 wherein the second width is less than or equal to about one-third of the first width.

7. The integrated assembly of claim 1 wherein each of the lower source/drain regions has a top surface at a third height, and wherein the second height is greater than or equal to the third height.

8. The integrated assembly of claim 7 wherein each of the wordlines has a bottom surface at a fourth height, and wherein the second height is less than the fourth height.

9. The integrated assembly of claim 1 wherein the digit lines comprise first conductive material, the shield lines comprise second conductive material and the wordlines comprise third conductive material; and wherein at least one of the first, second and third conductive materials is different from at least one other of the first, second and third conductive materials.

10. The integrated assembly of claim 1 wherein the digit lines comprise first conductive material, the shield lines comprise second conductive material and the wordlines comprise third conductive material; wherein the first, second and third conductive materials are a same composition; and wherein said same composition comprises metal.

11. The integrated assembly of claim 1 wherein the storage elements are comprised by memory cells of a memory array; wherein the digit lines extend along columns of the memory array and the wordlines extend along rows of the memory array; and further comprising a metal-containing reference structure under the memory array; each of the shield lines having a bottom surface directly adjacent to an upper surface of the metal-containing reference structure.

12. The integrated assembly of claim 1 wherein the storage elements are comprised by memory cells of a memory array; wherein the digit lines extend along columns of the memory array and the wordlines extend along rows of the memory array; wherein each of the shield lines has an end along a peripheral edge of the memory array; and further comprising:
a reference structure offset from the memory array; and
interconnects extending from the ends of the shield lines to the reference structure.

13. The integrated assembly of claim 12 wherein the reference structure is a metal-containing plate.

14. The integrated assembly of claim 12 wherein the reference structure is vertically offset from the memory array.

15. The integrated assembly of claim 12 wherein the reference structure is laterally offset from the memory array.

16. The integrated assembly of claim 12 wherein at least a portion of the reference structure is laterally offset from the memory array and is also vertically offset from the memory array.

17. The integrated assembly of claim 12 wherein the memory array is within a memory deck of a vertically-stacked arrangement of decks.

18. The integrated assembly of claim 17 wherein the vertically-stacked arrangement of decks includes a lower deck under the memory deck; the lower deck comprising control circuitry which is coupled with circuitry of the memory deck.

19. The integrated assembly of claim 18 wherein the reference structure is along the lower deck.

20. The integrated assembly of claim 1 wherein the storage elements are comprised by memory cells of a memory array; wherein the digit lines extend along columns of the memory array and the wordlines extend along rows of the memory array; wherein each of the shield lines has a first end and has a second end in opposing relation to the first end; and further comprising:
a first reference structure laterally offset from a first side of the memory array;
a second reference structure laterally offset from a second side of the memory array;
first interconnects extending from the first ends of the shield lines to the first reference structure; and
second interconnects extending from the second ends of the shield lines to the second reference structure.

21. The integrated assembly of claim 1 wherein the storage elements are comprised by memory cells of a memory array; wherein the digit lines extend along columns of the memory array and the wordlines extend along rows of the memory array; wherein each of the shield lines has a first end and has a second end in opposing relation to the first end; and further comprising:
a first reference structure laterally offset from a first side of the memory array;
a second reference structure laterally offset from a second side of the memory array;
first interconnects extending from the first ends of a first set of the shield lines to the first reference structure; and
second interconnects extending from the second ends of a second set of the shield lines to the second reference structure; the second set comprising different shield l

Assignees

• Micron Technology Inc

Inventors

• Tang Sanh D
• Pulugurtha Srinivas
• Hill Richard J
• Gao Yunfei
• Tapias Nicholas R
• Yang Litao
• Liu Haitao

Classifications

• H01L27/10802

  Electricity · mapped topic

• H01L27/10876

  Electricity · mapped topic

• H01L27/10841 Primary

  Electricity · mapped topic

• H10B12/30 Primary

  DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells · CPC title

• H10B12/48

  Data lines or contacts therefor · CPC title