Semiconductor device and method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-11069591-B2
Application number	US-201916559927-A
Country	US
Kind code	B2
Filing date	Sep 4, 2019
Priority date	Nov 16, 2004
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

A semiconductor device includes a semiconductor chip having a passivation film, a stress relieving layer provided on the passivation film, and a groove formed in a periphery of a surface of the semiconductor chip, the groove being provided inside of an edge of the semiconductor chip, wherein the stress relieving layer is partly disposed in the groove.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate:
a groove formed at an edge of the semiconductor substrate so that part of the groove is exposed at an outer edge of the semiconductor substrate;
a passivation film formed over the semiconductor substrate;
an external insulating layer formed over the passivation film, part of the external insulating layer intruding into the groove;
a ball terminal formed at the surface of the semiconductor device;
an opening formed through the passivation film at a location thereon; and
a wiring formed through the opening to connect the semiconductor substrate and the ball terminal,
wherein the passivation film formed next to the groove has a lateral surface and a vertical surface, the external insulating layer intrudes into the groove and is disposed in contact with both of the lateral surface and the vertical surface of the passivation film formed next to the groove.

2. The semiconductor device according to claim 1 , wherein the groove is a rectangular shape approximately in a sectional view.

3. The semiconductor device according to claim 2 , wherein the external insulating layer contacts with a lateral face of the groove directly without the passivation film.

4. The semiconductor device according to claim 3 , wherein the wiring is made of a material including copper.

5. The semiconductor device according to claim 4 , wherein the passivation is made of a material including nitride.

6. The semiconductor device according to claim 5 , wherein the ball terminal is a solder ball.

7. The semiconductor device according to claim 6 , wherein the semiconductor device is a quadrangle shape in a plain view.

8. The semiconductor device according to claim 7 , further comprising an internal insulating layer formed over the substrate and below the wiring layer.

9. The semiconductor device according to claim 8 , wherein the internal insulating layer is made of a material including a resin.

10. The semiconductor device according to claim 9 , wherein the semiconductor substrate is made of silicon.

11. The semiconductor device according to claim 10 , wherein the internal insulating layer is formed at least to absorb a stress to the semiconductor device.

12. The semiconductor device according to claim 11 , wherein the semiconductor device is formed as a wafer level chip size package.

13. The semiconductor device according to claim 12 , wherein the groove is formed to surround the semiconductor device.

14. The semiconductor device of claim 1 , wherein the wiring layer connects to the ball at a different location over the substrate than the location of the opening.

15. A semiconductor device, comprising:
a semiconductor substrate and having peripheral edges;
a groove formed on at least one peripheral edge of the semiconductor substrate and exposing at least a portion of a vertical surface thereof proximate to and below an upper surface thereof;
a passivation film formed over the semiconductor substrate, and at least an edge thereof extending to the groove;
an opening formed through the passivation film at a location thereon;
a wiring formed above the passivation film and extending through the opening;
a ball terminal formed at the surface of the semiconductor device above the wiring layer and connected to the wiring layer at location thereon; and
an external insulating layer formed over at least a portion of the passivation film, part of the external insulating layer extending vertically into the groove;
wherein at least a portion of the upper surface of the peripheral edge of the passivation film and a lateral edge thereof proximate to the groove is exposed to the external insulating layer, such that the external insulating layer contacts the least a portion of the upper surface of the peripheral edge of the passivation film and the lateral edge thereof in addition to exposed portions of the substrate in the groove.

16. The semiconductor device of claim 15 , wherein location of the opening in the passivation film is different than the location of the ball terminal relative to the wiring layer.

17. The semiconductor device of claim 16 , wherein the wiring layer is a rewiring layer.

18. The semiconductor device of claim 15 , and further comprising a stress relieving layer formed above the substrate below the wiring layer and above the passivation film.

19. The semiconductor device of claim 15 , and further comprising an electrode disposed on the surface of the semiconductor substrate below the opening and connected to the wiring layer through the opening.

Assignees

• Rohm Co Ltd

Inventors

• Miyata Osamu
• Kasai Masaki
• Higuchi Shingo

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W74/40

  characterised by their materials · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/9223

  with redistribution layers [RDL] · CPC title