Semiconductor device and method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-8928156-B2
Application number	US-201414306327-A
Country	US
Kind code	B2
Filing date	Jun 17, 2014
Priority date	Nov 16, 2004
Publication date	Jan 6, 2015
Grant date	Jan 6, 2015

Abstract

An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip. The sealing resin layer extends to a side surface of the passivation film to cover the side surface.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor chip having a passivation film on part of a front surface thereof which is a functional surface;
a stress relieving layer having an upper surface and a side surface provided on the passivation film;
a sealing resin layer provided on the stress relieving layer for sealing the front surface of the semiconductor chip, the sealing resin layer extending to a side surface of the stress relieving layer; and
a connecting layer provided on the upper surface of the stress relieving layer, the connecting layer having a side surface positioned inside of the stress relieving layer such that the upper surface of the stress relieving layer is partly exposed;
wherein the sealing resin layer is in direct contact with the semiconductor chip without the passivation film and in contact with the upper surface of the stress relieving layer, and
the sealing resin layer entirely covers the stress relieving layer, the passivation film and the connecting layer.

2. The semiconductor device according to claim 1 , further comprising a metal ball disposed on the sealing resin layer.

3. The semiconductor device according to claim 1 , wherein the semiconductor chip includes a semiconductor substrate of silicon.

4. The semiconductor device according to claim 1 , wherein the semiconductor chip has a rectangular shape as seen in plan.

5. The semiconductor device according to claim 1 , wherein the passivation film contains at least one of silicon oxide and silicon nitride.

6. The semiconductor device according to claim 1 , wherein the passivation film has a pad opening to expose an electrode pad.

7. The semiconductor device according to claim 6 , wherein the pad opening exposes a part of an internal interconnection of a metal provided in the front surface of the semiconductor chip as the electrode pad.

8. The semiconductor device according to claim 7 , wherein the metal includes aluminum.

9. The semiconductor device according to claim 1 , wherein the stress relieving layer includes polyimide.

10. The semiconductor device according to claim 1 , wherein the connecting layer is electrically connected to an electrode pad through a through-hole formed in the stress relieving layer at a position opposed to the electrode pad, and the electrode pad is exposed through a pad opening formed in the passivation film.

11. The semiconductor device according to claim 1 , wherein the sealing resin layer includes an epoxy resin.

12. A semiconductor device comprising:
a semiconductor chip having a passivation film on part of a front surface thereof which is a functional surface;
a stress relieving layer having an upper surface and a side surface provided on the passivation film;
a sealing resin layer provided on the stress relieving layer for sealing the front surface of the semiconductor chip, the sealing resin layer extending to a side surface of the stress relieving layer; and
a connecting member provided on the upper surface of the stress relieving layer, the connecting member having a side surface positioned inside of the stress relieving layer such that the upper surface of the stress relieving layer is partly exposed;
wherein the sealing resin layer is in direct contact with the semiconductor chip without the passivation film and in contact with the upper surface of the stress relieving layer, and
the sealing resin layer entirely covers the stress relieving layer, the passivation film and the connecting member.

13. The semiconductor device according to claim 12 , further comprising a metal ball disposed on the sealing resin layer.

14. The semiconductor device according to claim 12 , wherein the semiconductor chip includes a semiconductor substrate of silicon.

15. The semiconductor device according to claim 12 , wherein the semiconductor chip has a rectangular shape as seen in plan.

16. The semiconductor device according to claim 12 , wherein the passivation film contains at least one of silicon oxide and silicon nitride.

17. The semiconductor device according to claim 12 , wherein the passivation film has a pad opening to expose an electrode pad.

18. The semiconductor device according to claim 17 , wherein the pad opening exposes a part of an internal interconnection of a metal provided in the front surface of the semiconductor chip as the electrode pad.

19. The semiconductor device according to claim 18 , wherein the metal includes aluminum.

20. The semiconductor device according to claim 12 , wherein the stress relieving layer includes polyimide.

21. The semiconductor device according to claim 12 , wherein the connecting member is electrically connected to an electrode pad through a through-hole formed in the stress relieving layer at a position opposed to the electrode pad, and the electrode pad is exposed through a pad opening formed in the passivation film.

22. The semiconductor device according to claim 12 , wherein the sealing resin layer includes an epoxy resin.

Assignees

• Rohm Co Ltd

Inventors

• Miyata Osamu
• Kasai Masaki
• Higuchi Shingo

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W74/40

  characterised by their materials · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/9223

  with redistribution layers [RDL] · CPC title