Semiconductor device and method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-9601441-B2
Application number	US-201615059278-A
Country	US
Kind code	B2
Filing date	Mar 2, 2016
Priority date	Nov 16, 2004
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip, a groove formed in a periphery of a surface of the semiconductor chip being tapered toward a rear surface of the semiconductor chip, wherein the sealing resin layer is partly disposed in the groove.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor chip having a passivation film;
a sealing resin layer provided over the passivation film; and
a groove formed in a periphery of a front surface of the semiconductor chip, a width of the groove, as measured in parallel to the front surface, becomes gradually narrower towards a rear surface of the semiconductor chip, wherein
the sealing resin layer is partly disposed in the groove.

2. The semiconductor device according to claim 1 , wherein the groove is provided along an outermost peripheral edge of the front surface of the semiconductor chip.

3. The semiconductor device according to claim 2 , wherein
the width of the groove as measured within a plane containing the front surface of the semiconductor chip is greater than 5 μm, and
a depth of the groove is greater than 3 μm and smaller than 50 μm as measured perpendicularly to the plane.

4. The semiconductor device according to claim 1 , wherein the groove has a triangular sectional shape.

5. The semiconductor device according to claim 1 , wherein the semiconductor chip has a device formation region and the groove surrounds a device formation region of the semiconductor chip in a plan view.

6. The semiconductor device according to claim 1 , further comprising an interlayer film provided between the passivation film and a semiconductor substrate serving as a base of the semiconductor chip, wherein
the groove extends to below the interlayer film, and
side surfaces of the passivation film and the interlayer film are exposed in the groove.

7. The semiconductor device according to claim 1 , wherein the semiconductor chip includes a semiconductor substrate of silicon.

8. The semiconductor device according to claim 1 , wherein the semiconductor chip has a rectangular shape in a plan view of the semiconductor device.

9. The semiconductor device according to claim 1 , wherein the passivation film contains at least one of silicon oxide and silicon nitride.

10. The semiconductor device according to claim 1 , further comprising an electrode pad that is exposed by a pad opening in the passivation film.

11. The semiconductor device according to claim 1 , further comprising a metal internal interconnection provided in the front surface of the semiconductor chip, a part of the internal interconnection being exposed by a pad opening in the passivation film as an electrode pad.

12. The semiconductor device according to claim 11 , wherein the internal interconnection includes aluminum.

13. The semiconductor device according to claim 1 , wherein the sealing resin layer includes an epoxy resin.

14. The semiconductor device according to claim 1 , further comprising a metal ball disposed on the sealing resin layer.

15. The semiconductor device according to claim 1 , further comprising a stress relieving layer provided between the passivation film and the sealing resin layer.

Assignees

• Rohm Co Ltd

Inventors

• Miyata Osamu
• Kasai Masaki
• Higuchi Shingo

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W74/40

  characterised by their materials · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/9223

  with redistribution layers [RDL] · CPC title