Semiconductor device and method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-9312228-B2
Application number	US-201514795955-A
Country	US
Kind code	B2
Filing date	Jul 10, 2015
Priority date	Nov 16, 2004
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip. The sealing resin layer extends to a side surface of the passivation film to cover the side surface.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor chip having a passivation film;
a stress relieving layer provided on the passivation film; and
a groove formed in a periphery of a surface of the semiconductor chip, the groove provided inside of an edge of the semiconductor chip, wherein
the stress relieving layer is partly disposed in the groove.

2. The semiconductor device according to claim 1 , wherein the stress relieving layer extends to a side surface of the passivation film to cover the side surface.

3. The semiconductor device according to claim 2 , wherein
the groove surrounds a device formation region of the semiconductor chip in a plan view, and
the passivation film includes a center portion covering the device formation region and a peripheral portion disposed on opposite sides of the groove.

4. The semiconductor device according to claim 1 , further comprising a sealing resin layer extending to a side surface of the stress relieving layer to cover the side surface.

5. The semiconductor device according to claim 1 , wherein
the stress relieving layer extends to a side surface of the passivation film to cover the side surface,
the groove surrounds a device formation region of the semiconductor chip in a plan view,
the passivation film includes a center portion covering the device formation region and a peripheral portion disposed on opposite sides of the groove,
the stress relieving layer selectively covers the center portion of the passivation, and
the semiconductor device further includes a sealing resin layer extending to a side surface of the stress relieving layer to cover the side surface and the peripheral portion of the passivation film.

6. The semiconductor device according to claim 5 , wherein a depth of the groove is larger than a width of the peripheral portion of the passivation film.

7. The semiconductor device according to claim 1 , wherein the semiconductor chip includes a semiconductor substrate of silicon.

8. The semiconductor device according to claim 1 , wherein the semiconductor chip has a rectangular shape as seen in plan.

9. The semiconductor device according to claim 1 , wherein the passivation film contains at least one of silicon oxide and silicon nitride.

10. The semiconductor device according to claim 1 , wherein the passivation film has a pad opening to expose an electrode pad.

11. The semiconductor device according to claim 10 , wherein the pad opening exposes a part of an internal interconnection of a metal provided in a front surface of the semiconductor chip as the electrode pad.

12. The semiconductor device according to claim 11 , wherein the internal interconnection includes aluminum.

13. The semiconductor device according to claim 1 , wherein the stress relieving layer includes polyimide.

14. The semiconductor device according to claim 4 , wherein the sealing resin layer includes an epoxy resin.

15. The semiconductor device according to claim 4 , further comprising a metal ball disposed on the sealing resin layer.

Assignees

• Rohm Co Ltd

Inventors

• Miyata Osamu
• Kasai Masaki
• Higuchi Shingo

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W74/40

  characterised by their materials · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/9223

  with redistribution layers [RDL] · CPC title