Apparatus and methods for qualifying HEMT FET devices

Patent metadata

Field	Value
Publication number	US-9476933-B2
Application number	US-201414547849-A
Country	US
Kind code	B2
Filing date	Nov 19, 2014
Priority date	Dec 9, 2013
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

A method includes coupling a gate pulse generator to a gate terminal of a power transistor device under test, coupling a drain pulse generator to a drain terminal of the power transistor device under test; for a first set of test conditions, activating the drain pulse generator for each of the test conditions to apply a voltage pulse to the drain terminal, and for each of the test conditions, applying a voltage pulse to the gate terminal, the gate pulse rising only after the drain pulse falls below a predetermined threshold; for a second set of test conditions, applying a voltage pulse to the drain terminal, and applying a voltage pulse to the gate terminal, the drain pulse generator and the gate pulse generator both being active so that there is some overlap; and measuring the drain current into the power transistor device under test. An apparatus is disclosed.

First claim

What is claimed is:

1. A test method, comprising:
coupling a gate pulse generator to a gate terminal of a power transistor device under test, coupling a drain pulse generator to a drain terminal of the power transistor device under test, and coupling a source terminal of the power transistor device under test to a ground potential;
coupling a current monitor to the drain terminal of the power transistor device under test;
for a first set of test conditions, activating the drain pulse generator for each of the test conditions to apply a voltage pulse to the drain terminal of the power transistor device under test, and for each of the test conditions, applying a voltage pulse to the gate terminal of the power transistor device from the gate pulse generator, the gate pulse rising only after the drain pulse falls below a predetermined threshold for each of the first set of test conditions;
for each of the first set of test conditions, measuring the drain current of the power transistor device under test with the drain current monitor;
for a second set of test conditions, activating the drain pulse generator and applying a voltage pulse to the drain terminal of the power transistor device under test, and applying a voltage pulse to the gate terminal of the power transistor device under test as the drain pulse falls for each of the second set of test conditions, the drain pulse generator and the gate pulse generator both being active for a portion of the second set of test conditions so that there is some overlap between the voltage pulse applied to the drain terminal and the voltage pulse applied to the gate terminal; and
for each of the second set of test conditions, measuring the drain current into the power transistor device under test with the drain current monitor.

2. The method of claim 1 , and further comprising:
storing the drain current measurements for the first set of test conditions, and storing the drain current measurements for the second set of test conditions; and
comparing the stored drain current measurements to a set of predicted drain current measurements, and determining whether the drain current of the power transistor device under test is within a predetermined threshold of the predicted drain currents.

3. The method of claim 1 , and further comprising:
indicating the power transistor device under test is a qualified device, responsive to the determining.

4. The method of claim 1 , wherein the power transistor device under test further comprises a gallium arsenide (GaN) field effect transistor (FET).

5. The method of claim 4 , wherein the GaN FET further comprises an AlGaN portion located in a channel region, a GaN portion formed over the AlGaN portion in the channel region, a gate dielectric layer formed over the GaN portion, and the gate terminal comprises a gate electrode formed over the gate dielectric.

6. The method of claim 1 , wherein the power transistor device under test further comprises a gallium arsenide (GaAs) field effect transistor (FET).

7. The method of claim 6 , wherein the GaAs FET further comprises an AlGaAs portion located in a channel region, a GaAs portion formed over the AlGaAs portion in the channel region, a gate dielectric layer formed over the GaAs portion, and the gate terminal comprises a gate electrode formed over the gate dielectric.

8. The method of claim 1 , wherein the power transistor device is disposed within a packaged integrated circuit.

9. The method of claim 1 , wherein the power transistor device under test is one of a plurality of power transistor devices disposed on a semiconductor wafer.

10. The method of claim 1 , and further comprising:
outputting the measured drain currents to test equipment having a graphical display; and
displaying the drain current plotted against the gate voltage and drain voltage, to depict load lines of the power transistor under test.

11. The method of claim 1 , wherein the first set of test conditions further comprises activating the gate pulse generator to place a voltage pulse on the gate terminal, wherein the gate voltage varies between 0 Volts and a predetermined maximum magnitude, varying the gate voltage in steps for a plurality of test conditions.

12. The method of claim 11 , wherein the second set of test conditions further comprises activating the gate pulse generator to place a voltage pulse on the gate terminal overlapping the voltage pulse on the drain terminal, and for each of a plurality of test conditions, the voltage pulse applied to the gate terminal varies from 0 Volts to a maximum voltage magnitude in predetermined steps.

13. A method for manufacturing power FET devices, comprising:
providing a semiconductor wafer comprising a plurality of integrated circuits formed thereon, each of the integrated circuits having at least one power FET device comprising a high electron mobility transistor (HEMT) having a gate, a drain and a source terminal;
providing a probe card having conductive probes configured to electrically contact the gate, drain and source terminals of the at least one power FET device on one or more of the integrated circuits on the semiconductor wafer, and placing the probe card proximate to and in alignment with the semiconductor wafer;
moving at least one of the semiconductor wafer and the probe card to establish electrical contact between ends of the conductive probes and the semiconductor wafer;
coupling a gate pulse generator to a probe that is in electrical contact with a gate terminal of the power FET device on the semiconductor wafer, coupling a drain pulse generator to a probe that is in electrical contact with the drain terminal of the power FET device and coupling a ground potential to a probe that is in electrical contact with the source terminal of the power FET device;
for a first set of test conditions, activating the drain pulse generator and applying a voltage pulse to the drain terminal of the power FET, and for each of the first set of test conditions, activating the gate pulse generator and applying a voltage pulse to the gate terminal of the power FET, the gate pulse rising only after the drain pulse falls to a predetermined low voltage for each test condition so the gate and drain voltage pulses never overlap;
for each of the first set of test conditions, measuring the drain current of the power FET device with a drain current monitor;
for a second set of test conditions, activating the drain pulse generator and applying a voltage pulse to the drain terminal of the power FET, and activating the gate pulse generator and applying a voltage pulse to the gate terminal of the power FET as the drain pulse falls for each of the second set of test conditions, the drain pulse generator and the gate pulse generator both being active for a portion of each of the second set of test conditions, so that there is some overlap between the voltage pulse applied to the drain terminal and the voltage pulse applied to the gate terminal; and
for each of the second set of test conditions, measuring the drain current into the power FET with the drain current monitor.

14. The method of claim 13 , wherein each of the power FET devices further comprises one selected from the group consisting essentially of a gallium nitride heterojunction FET transistor and a gallium arsenide heterojunction FET transistor.

15. The method of claim 13 , and further comprising:
storing the drain current measurements for the first set of test conditions, and storing the drain current measurements for the second set of test conditions; and
comparing the stored drain current measurements to a set of predicted

Assignees

• Texas Instruments Inc

Inventors

• Joh Jungwoo
• Krishnan Srikanth
• Pendharkar Sameer

Classifications

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D30/4755

  having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs · CPC title

• G01R31/2621 Primary

  for testing field effect transistors, i.e. FET's · CPC title

• H01L29/7787

  Electricity · mapped topic

• H01L29/2003

  Electricity · mapped topic