High-resolution power electronics measurements

Patent metadata

Field	Value
Publication number	US-10094863-B2
Application number	US-201615058444-A
Country	US
Kind code	B2
Filing date	Mar 2, 2016
Priority date	Mar 2, 2016
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

Disclosed examples include systems to determine an on-state impedance of a high voltage transistor, and measurement circuits to measure the drain voltage of a drain terminal of the high voltage transistor during switching, including an attenuator circuit to generate an attenuator output signal representing a voltage across the high voltage transistor when the high voltage transistor is turned on, and a differential amplifier to provide an amplified sense voltage signal according to the attenuator output signal. The attenuator circuit includes a clamp transistor coupled with the drain terminal of the high voltage transistor to provide a sense signal to a first internal node, a resistive voltage divider circuit to provide the attenuator output signal based on the sense signal, and a first clamp circuit to limit the sense signal voltage when the high voltage transistor is turned off.

First claim

The following is claimed:

1. A measurement circuit to measure a voltage of a drain terminal of a high voltage transistor during switching, the measurement circuit comprising:
an attenuator circuit to generate an attenuator output signal representing a voltage across the high voltage transistor when the high voltage transistor is turned on, the attenuator circuit comprising:
a clamp transistor having a first terminal coupled with the drain terminal of the high voltage transistor through a first resistor, a second terminal to provide a sense signal to a first internal node, and a control terminal,
a bias circuit to provide a first bias signal to the control terminal based on a first supply voltage to turn the clamp transistor on when the high voltage transistor is turned on,
a first voltage divider circuit, including an attenuator output node to provide the attenuator output signal based on the sense signal from the clamp transistor, a first divider resistor coupled between the first internal node and the attenuator output node, and a second divider resistor coupled between the attenuator output node and a constant voltage node, and
a Zener diode coupled between the first internal node and the constant voltage node to limit a voltage between the first internal node and the constant voltage node when the high voltage transistor is turned off; and
a differential amplifier, including a first input coupled with the attenuator output node to receive the attenuator output signal, a second input coupled with a reference voltage node, and an output to provide an amplified sense voltage signal representing the voltage across the high voltage transistor when the high voltage transistor is turned on.

2. The measurement circuit of claim 1 , further comprising a clamp circuit to condition the attenuator output signal, the clamp circuit comprising:
a second voltage divider circuit, including a third divider resistor coupled between a second supply voltage and a second internal node, and a fourth divider resistor coupled between the second internal node and the constant voltage node; and
a diode to limit a voltage of the attenuator output node, the diode including an anode coupled with the attenuator output node, and a cathode coupled with the second internal node.

3. The measurement circuit of claim 2 , further comprising a compensation capacitor to compensate a capacitance of the first input of the differential amplifier, the compensation capacitor including a first terminal connected to the first internal node, and a second terminal connected to the attenuator output node.

4. The measurement circuit of claim 3 , wherein the first divider resistor is adjustable.

5. The measurement circuit of claim 4 , wherein the bias circuit includes a second resistor coupled between the first supply voltage and the control terminal of the clamp transistor, a third resistor coupled between the control terminal of the clamp transistor and the constant voltage node, and a bias circuit capacitor coupled between the control terminal of the clamp transistor and the constant voltage node to reduce voltage spikes on the control terminal of the clamp transistor during switching of the high voltage transistor.

6. The measurement circuit of claim 3 , wherein the bias circuit includes a second resistor coupled between the first supply voltage and the control terminal of the clamp transistor, a third resistor coupled between the control terminal of the clamp transistor and the constant voltage node, and a bias circuit capacitor coupled between the control terminal of the clamp transistor and the constant voltage node to reduce voltage spikes on the control terminal of the clamp transistor during switching of the high voltage transistor.

7. The measurement circuit of claim 2 , wherein the first divider resistor is adjustable.

8. The measurement circuit of claim 2 , wherein the bias circuit includes a second resistor coupled between the first supply voltage and the control terminal of the clamp transistor, a third resistor coupled between the control terminal of the clamp transistor and the constant voltage node, and a bias circuit capacitor coupled between the control terminal of the clamp transistor and the constant voltage node to reduce voltage spikes on the control terminal of the clamp transistor during switching of the high voltage transistor.

9. The measurement circuit of claim 1 , further comprising a compensation capacitor to compensate a capacitance of the first input of the differential amplifier, the compensation capacitor including a first terminal connected to the first internal node, and a second terminal connected to the attenuator output node.

10. The measurement circuit of claim 9 , wherein the first divider resistor is adjustable.

11. The measurement circuit of claim 9 , wherein the bias circuit includes a second resistor coupled between the first supply voltage and the control terminal of the clamp transistor, a third resistor coupled between the control terminal of the clamp transistor and the constant voltage node, and a bias circuit capacitor coupled between the control terminal of the clamp transistor and the constant voltage node to reduce voltage spikes on the control terminal of the clamp transistor during switching of the high voltage transistor.

12. The measurement circuit of claim 1 , wherein the first divider resistor is adjustable.

13. The measurement circuit of claim 12 , wherein the bias circuit includes a second resistor coupled between the first supply voltage and the control terminal of the clamp transistor, a third resistor coupled between the control terminal of the clamp transistor and the constant voltage node, and a bias circuit capacitor coupled between the control terminal of the clamp transistor and the constant voltage node to reduce voltage spikes on the control terminal of the clamp transistor during switching of the high voltage transistor.

14. The measurement circuit of claim 1 , wherein the bias circuit includes a second resistor coupled between the first supply voltage and the control terminal of the clamp transistor, a third resistor coupled between the control terminal of the clamp transistor and the constant voltage node, and a bias circuit capacitor coupled between the control terminal of the clamp transistor and the constant voltage node to reduce voltage spikes on the control terminal of the clamp transistor during switching of the high voltage transistor.

15. A system to determine an on-state impedance of a high voltage transistor during switching, the system comprising:
a test circuit to receive the high voltage transistor;
a drive circuit to provide a switching control signal to a gate control terminal of the high voltage transistor to alternately conduct and block current from a high voltage supply in the test circuit;
a current sense circuit to provide a current sense signal representing a current flowing in the high voltage transistor;
an attenuator circuit to generate an attenuator output signal representing a voltage across the high voltage transistor when the high voltage transistor is turned on, the attenuator circuit comprising:
a clamp transistor having a first terminal coupled with a drain terminal of the high voltage transistor through a first resistor, a second terminal to provide a sense signal to a first internal node, and a control terminal,
a bias circuit to provide a first bias signal to the control terminal based on a first supply voltage to turn the clamp transistor on when the high voltage transistor is turned on,
a first voltage divider circuit, including an attenuator output nod

Assignees

• Texas Instruments Inc

Inventors

• Bahl Sandeep R
• Smith Grant L
• Ruiz Flores Daniel

Classifications

• G01R19/0084

  Measuring voltage only · CPC title

• G01R31/2621 Primary

  for testing field effect transistors, i.e. FET's · CPC title

• G01R31/2617

  for measuring switching properties thereof · CPC title

• G01R31/2639

  for testing field-effect devices, e.g. of MOS-capacitors (G01R31/2621 takes precedence) · CPC title

• G01R27/02 Primary

  Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant (by measuring phase angle only G01R25/00) · CPC title