Systems and methods for designing integrated circuits

Patent metadata

Field	Value
Publication number	US-11062067-B2
Application number	US-201916565634-A
Country	US
Kind code	B2
Filing date	Sep 10, 2019
Priority date	Sep 10, 2018
Publication date	Jul 13, 2021
Grant date	Jul 13, 2021

Abstract

System and methods to generate a circuit design for an integrated circuit using only allowable pairs of connected logic stages. The allowable pairs of connected logic stages are those pairs of connected logic stages with a static noise margin (SNM) above an SNM threshold. Also presented is a 16-bit microprocessor made entirely from carbon nanotube field effect transistors (CNFET) having such allowable pair of connected logic stages.

First claim

The invention claimed is:

1. A system for designing an integrated circuit, the system comprising:
a database to store indications of logic stages for the integrated circuit; and
a processor, operably coupled to the database, to:
for each pair of logic stages, compute a static noise margin (SNM), the SNM representing immunity to noise of that pair of logic stages when connected and when at least one logic stage of that pair of logic stages comprises a metallic carbon nanotube (m-CNT);
set an initial value of a SNM threshold based on a predetermined minimum SNM value and a predetermined maximum SNM value;
identify allowable pairs of connected logic stages as those pairs of connected logic stages with an SNM above the SNM threshold;
generate a circuit design for the integrated circuit using only the allowable pairs of connected logic stages; and
determine a performance parameter for the integrated circuit based on the circuit design.

2. The system of claim 1 , wherein the processor is further configured to:
determine an adjusted SNM threshold based on a likelihood that the circuit design meets a predetermined noise criterion;
identify adjusted allowable pairs of connected logic stages as those pairs of connected logic stages with an SNM above the adjusted SNM threshold; and
generate an adjusted circuit design for the integrated circuit using only the adjusted allowable pairs of connected logic stages.

3. The system of claim 1 , wherein the performance parameter is at least one of power consumption, switching delay, or surface area, and wherein the processor is further configured to:
calculate an adjusted SNM threshold based on a likelihood that the circuit design meets a predetermined noise criterion;
iteratively repeat said identify, generate, calculate steps based on the adjusted SNM threshold to generate a set of circuit designs until two circuit designs in the set of circuit designs include the same allowable pairs of connected logic stages; and
select a circuit design of the set of circuit designs that (a) has a 99% likelihood that it meets the maximum noise criterion and (b) has the lowest value among the set of circuit designs for the at least one of the power consumption, switching delay, or surface area.

4. The system of claim 1 , wherein the performance parameter is at least one of power consumption, switching delay, or surface area.

5. The system of claim 1 , further comprising:
a manufacturing unit, operably coupled to the database, to manufacture an integrated circuit based on the circuit design.

6. The system of claim 1 , wherein the plurality of logic stages includes at least one carbon nanotube field-effect transistor (CNFET) and the integrated circuit has a semiconductor-carbon nanotube (s-CNT) purity of less than 100%.

7. The system of claim 1 , wherein the circuit design includes at least one thousand connected logic stages.

8. The system of claim 1 , wherein the processor is configured to compute the SNM for the pair of connected logic stages by measuring voltage-transfer characteristics for that pair of connected logic stages for different numbers of metallic-carbon nanotubes (m-CNTs) in that pair of connected logic stages.

9. A method for designing an integrated circuit, the method comprising:
a) for each pair of connected logic stages of a plurality of connected logic stages, computing a static noise margin (SNM), the SNM representing immunity to noise of that pair of connected logic stages and when at least one logic stage of that pair of connected logic stages comprises a metallic carbon nanotube (m-CNT);
b) setting an initial value of a SNM threshold based on a predetermined minimum SNM value and a predetermined maximum SNM value;
c) identifying allowable pairs of connected logic stages as those pairs of connected logic stages with an SNM above the SNM threshold;
d) generating a circuit design for an integrated circuit using only the allowable pairs of connected logic stages;
e) adjusting the SNM threshold based on the likelihood that the circuit design meets a predetermined noise criterion; a
f) iteratively repeating steps (c), (d), and (e) based on the adjusted SNM threshold to generate a set of circuit designs; and
g) when two circuit designs in the set of circuit designs include the same allowable pairs of logic stages, selecting a circuit design of the set of circuit designs that has 1) a 99% likelihood of meeting the maximum noise criterion and 2) the lowest value among the set of circuit designs for power consumption, switching delay, and/or surface area.

10. The method of claim 9 , further comprising manufacturing the integrated circuit based on the selected circuit design.

11. The method of claim 10 , wherein the integrated circuit has a semiconductor-carbon nanotube (s-CNT) purity of at most 99.99%.

12. The method of claim 9 , wherein the integrated circuit includes at least one thousand connected logic stages.

13. The method of claim 9 , wherein the integrated circuit includes at least one million connected logic stages.

14. The method of claim 9 , wherein (b) includes estimating voltage-transfer curves for that pair of logic stages for different numbers of metallic-carbon nanotubes (m-CNTs) in at least one connected logic stage of that pair of connected logic stages.

Assignees

• Massachusetts Inst Technology

Inventors

• Hills Gage Krieger
• Shulaker Max

Classifications

• G06F2119/02

  Reliability analysis or reliability optimisation; Failure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA] · CPC title

• G06F2119/10

  Noise analysis or noise optimisation · CPC title

• G06F2111/04

  Constraint-based CAD · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/337

  Design optimisation · CPC title