Sample rate conversion circuit with noise shaping modulation

Patent metadata

Field	Value
Publication number	US-11050435-B1
Application number	US-202016858491-A
Country	US
Kind code	B1
Filing date	Apr 24, 2020
Priority date	Apr 24, 2020
Publication date	Jun 29, 2021
Grant date	Jun 29, 2021

Abstract

Systems and methods for low power sample rate conversion are based on a noise shaping technique. A sample rate conversion circuit includes a clock synchronization circuit configured to receive an input sample sequence at a first sample rate and generate a valid sample sequence that is sampled at a second sample rate different from the first sample rate. The valid sample sequence may include valid samples from a registered sequence sampled at an oversampled rate greater than the first sample rate with invalid samples in the registered sequence being excluded from the valid sample sequence. The sample rate conversion circuit also includes a noise shaping circuit coupled to the clock synchronization circuit and configured to encode the valid sample sequence into a noise-shaped output sequence at the second sample rate by suppressing quantization noise from the valid sample sequence.

First claim

What is claimed is:

1. A system comprising:
a modulation source configured to modulate an input analog signal into an input sample sequence; and
a clock synchronization circuit configured to receive the input sample sequence at a first sample rate and generate a valid sample sequence that is sampled at a second sample rate different from the first sample rate, the valid sample sequence comprising valid samples from a registered sequence that is sampled at an oversampled rate greater than the first sample rate with invalid samples in the registered sequence being excluded from the valid sample sequence.

2. The system of claim 1 , further comprising:
a noise shaping circuit coupled to the clock synchronization circuit and configured to encode the valid sample sequence into a noise-shaped output sequence at the second sample rate by suppressing quantization noise from the valid sample sequence.

3. The system of claim 2 , wherein the clock synchronization circuit comprises:
a plurality of registers connected in series and configured to sample the input sample sequence at the oversampled rate for successive clock edges to provide the registered sequence; and
a sequence circuit coupled to the plurality of registers and configured to detect transitions in values of the registered sequence and identify the values at the transitions as the invalid samples for filtration.

4. The system of claim 3 , wherein the sequence circuit comprises:
a sequence detect circuit configured to detect the invalid samples at a first clock edge of the successive clock edges and the valid samples at a second clock edge of the successive clock edges that is subsequent to the first clock edge; and
a sequence filter configured to filter the invalid samples with the valid samples being passed to the valid sample sequence.

5. The system of claim 3 , wherein the plurality of registers is clocked at the oversampled rate and the sequence circuit is clocked at the second sample rate.

6. The system of claim 2 , wherein the noise shaping circuit comprises a delta-sigma modulator, wherein the delta-sigma modulator is a kth-order delta-sigma modulator, where k is greater than 1.

7. The system of claim 2 , wherein the modulation source comprises a pulse density modulator configured to modulate the input analog signal into a sampled signal as a sequence of single bits at the first sample rate.

8. The system of claim 7 , further comprising:
a pre-amplifier coupled to an input to the pulse density modulator and configured to amplify the input analog signal into an amplified analog signal, wherein the pulse density modulator modulates the amplified analog signal into the sampled signal; and
an oversampled interpolation filter coupled to an output of the pulse density modulator and configured to remove out-of-band aliased images from the sampled signal using one or more internal delays in the oversampled interpolation filter that operate at different sample frequencies.

9. The system of claim 8 , further comprising a decimation filter coupled to the noise shaping circuit and configured to downsample the noise-shaped output sequence at the second sample rate and provide a pulse code modulated signal with a downsampled rate by decimating the second sample rate by a factor of L, where L is a positive integer.

10. The system of claim 7 , further comprising:
a decimation filter coupled to the pulse density modulator and configured to downsample the sampled signal into a decimated signal by decimating the first sample rate by a factor of N, where N is a positive integer; and
an interpolation filter coupled to the decimation filter and to an input to the clock synchronization circuit and configured to produce the input sample sequence at the first sample rate by interpolating the decimated signal by the factor of N.

11. The system of claim 2 , further comprising:
a delta-sigma modulator configured to produce a sampled signal as a sequence of multi-bit words at the first sample rate divided by a factor of N, where N is a positive integer; and
an interpolation filter coupled to the delta-sigma modulator and to an input to the clock synchronization circuit and configured to produce the input sample sequence at the first sample rate by interpolating the sampled signal by the factor of N.

12. The system of claim 11 , further comprising a decimation filter coupled to the noise shaping circuit and configured to downsample the noise-shaped output sequence into a pulse code modulated signal by decimating the second sample rate by a factor of L, where L is a positive integer.

13. A sample rate converter comprising:
a modulation source configured to modulate an input analog signal into an input sample sequence;
a clock synchronization circuit configured to receive the input sample sequence at a first sample rate and generate a valid sample sequence that is sampled at a second sample rate different from the first sample rate, the valid sample sequence comprising valid samples from a sampled sequence that is sampled at an oversampled rate greater than the first sample rate with invalid samples in the sampled sequence being excluded from the valid sample sequence; and
a noise shaping circuit coupled to the clock synchronization circuit and configured to encode the valid sample sequence into a noise-shaped output sequence at the second sample rate by suppressing quantization noise from the valid sample sequence.

14. The sample rate converter of claim 13 , wherein the modulation source is a pulse density modulator configured to produce a modulated signal from the input analog signal.

15. The sample rate converter of claim 14 , further comprising:
a pre-amplifier coupled to an input to the pulse density modulator and configured to amplify the input analog signal into an amplified analog signal, wherein the pulse density modulator modulates the amplified analog signal into the modulated signal; and
an oversampled interpolation filter coupled to an output of the pulse density modulator and configured to produce the input sample sequence by removing out-of-band aliased images from the modulated signal using one or more internal delays in the oversampled interpolation filter that operate at different sample frequencies.

16. The sample rate converter of claim 15 , further comprising a decimation filter coupled to the noise shaping circuit and configured to downsample the noise-shaped output sequence at the second sample rate and provide a pulse code modulated signal with a downsampled rate by decimating the second sample rate by a factor of L, where L is a positive integer.

17. The sample rate converter of claim 14 , further comprising:
a decimation filter coupled to the pulse density modulator and configured to downsample the modulated signal into a decimated signal by decimating the first sample rate by a factor of N, where N is a positive integer; and
an interpolation filter coupled to the decimation filter and to an input to the clock synchronization circuit and configured to produce the input sample sequence at the first sample rate by interpolating the decimated signal by the factor of N.

18. The sample rate converter of claim 13 , wherein the modulation source is a delta-sigma modulator that is configured to produce a modulated signal from the input analog signal, and further comprising an interpolation filter coupled to the delta-sigma modulator and to an input to the clock synchronization circuit and configured to produce the input sample sequence at the first sample rate by interpolating the modulated si

Assignees

• Synaptics Inc

Inventors

• Poulsen Jens Kristian

Classifications

• H03M7/3004 Primary

  Digital delta-sigma modulation · CPC title

• H03M3/042

  with adaptable step size, e.g. adaptive differential pulse code modulation [ADPCM] · CPC title

• H03M3/402

  Arrangements specific to bandpass modulators · CPC title

• H03M3/344

  by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing · CPC title

• H03M3/498 Primary

  Variable sample rate · CPC title