Electrical circuit

Patent metadata

Field	Value
Publication number	US-9742427-B2
Application number	US-201615151236-A
Country	US
Kind code	B2
Filing date	May 10, 2016
Priority date	Nov 15, 2013
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

An electrical circuit includes a signal processing chain and a controller. The signal processing chain includes an integrator configured to integrate an input signal over an integration time. The controller is connected to a signal output of the signal processing chain to receive and evaluate an output signal of the signal processing chain. The controller is further configured to adapt the integration time based on the output signal.

First claim

The invention claimed is:

1. An electrical circuit comprising:
a signal processing chain comprising an integrator configured to integrate an input signal over an integration time; and
a controller connected to a signal output of the signal processing chain to receive and evaluate an output signal of the signal processing chain and configured to adapt the integration time based on the output signal, wherein the controller adapts the integration time such that a period of the fundamental wave of the input signal is an integer multiple of the mean integration time.

2. An electrical circuit comprising:
a signal processing chain comprising an integrator configured to integrate an input signal over an integration time; and
a controller connected to a signal output of the signal processing chain to receive and evaluate an output signal of the signal processing chain and configured to adapt the integration time based on the output signal, wherein the controller adapts the integration time to achieve synchronization of at least 90% between the integration time and a fundamental wave of the input signal in consideration of a division factor between a system clock of the electrical circuit and the fundamental wave.

3. The electrical circuit according to claim 1 , wherein the signal processing chain comprises a sigma-to-delta modulator.

4. The electrical circuit according to claim 3 , wherein the sigma-to-delta modulator is of n th order with n≧1.

5. The electrical circuit according to claim 1 , wherein the signal processing chain comprises a comparator coupled to the integrator.

6. The electrical circuit according to claim 1 , wherein the signal processing chain comprises a filter and/or decimation filter which comprises the integrator.

7. An electrical circuit comprising:
a signal processing chain comprising an integrator configured to integrate an input signal over an integration time; and
a controller connected to a signal output of the signal processing chain to receive and evaluate an output signal of the signal processing chain and configured to adapt the integration time based on the output signal, wherein the circuit is connected to an oscillator or comprises the oscillator which outputs an oscillation signal of constant frequency to the signal processing chain.

8. An electrical circuit comprising:
a signal processing chain comprising an integrator configured to integrate an input signal over an integration time; and
a controller connected to a signal output of the signal processing chain to receive and evaluate an output signal of the signal processing chain and configured to adapt the integration time based on the output signal, wherein the integral of the output signal over the integration time is proportional to the integration time.

9. The electrical circuit according to claim 8 , wherein the signal processing chain is coupled to a post-processing stage comprising a division formation element configured to divide the output signal of the signal processing chain by the integration time and to output a division value as a result.

10. The electrical circuit according to claim 9 , wherein the controller is coupled to the post-processing stage.

11. An electrical circuit comprising:
a signal processing chain comprising an integrator configured to integrate an input signal over an integration time; and
a controller connected to a signal output of the signal processing chain to receive and evaluate an output signal of the signal processing chain and configured to adapt the integration time based on the output signal, wherein the controller comprises a phase discriminator configured to evaluate the output signal regarding phase errors, and wherein the controller adapts the integration time such that the phase errors are minimized.

12. An electrical circuit comprising:
a signal processing chain comprising an integrator configured to integrate an input signal over an integration time; and
a controller connected to a signal output of the signal processing chain to receive and evaluate an output signal of the signal processing chain and configured to adapt the integration time based on the output signal, wherein the integrator is reset by a control signal output by the controller so that the integrator forms a new measurement value without any impact from past measurement values.

13. An electrical circuit comprising:
a signal processing chain comprising an integrator configured to integrate an input signal over an integration time; and
a controller connected to a signal output of the signal processing chain to receive and evaluate an output signal of the signal processing chain and configured to adapt the integration time based on the output signal, wherein the controller comprises a phase-locked loop which outputs a control signal by which the integration time of the integrator is controlled.

14. The electrical circuit according to claim 1 , wherein the signal processing chain is configured to supply a digital output signal based on an analog input signal.

15. A method for signal processing comprising:
integrating an input signal over an integration time by means of a signal processing chain which comprises an integrator;
receiving and evaluating an output signal of the signal processing chain; and
adapting the integration time based on the output signal, wherein the signal processing chain comprises a sigma-to-delta modulator.

16. A non-transitory digital storage medium having a computer program stored thereon to perform a method for signal processing comprising:
integrating an input signal over an integration time by means of a signal processing chain which comprises an integrator;
receiving and evaluating an output signal of the signal processing chain; and
adapting the integration time based on the output signal,

when said computer program is run by a computer.

Assignees

• Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E V

Inventors

• Hackner Michael
• Hohe Hans-Peter
• Sand Markus

Classifications

• H03M7/3004

  Digital delta-sigma modulation · CPC title

• H03M1/82

  with intermediate conversion to time interval · CPC title

• H03M3/496

  Details of sampling arrangements or methods · CPC title

• H03M1/1255

  Synchronisation of the sampling frequency or phase to the input frequency or phase · CPC title

• H03M1/50

  with intermediate conversion to time interval (H03M1/64 takes precedence) · CPC title