High-order sigma delta for a divider-less digital phase-locked loop

Patent metadata

Field	Value
Publication number	US-9571107-B2
Application number	US-201414317435-A
Country	US
Kind code	B2
Filing date	Jun 27, 2014
Priority date	Jun 27, 2014
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

Described herein are technologies related to an implementation of a divider-less digital phase-locked loop (DPLL) that includes a loop response matching a higher order sigma delta.

First claim

What is claimed is:

1. A divider-less phase-locked loop (PLL) system comprising:
a reference frequency oscillator configured to provide a reference signal;
a voltage controlled oscillator (VCO) configured to provide a feedback signal;
a time-to-digital converter (TDC) configured to receive the reference signal and the feedback signal, the TDC measures a time difference between the reference signal and the feedback signal; and
a sigma delta control unit that is coupled to the TDC, the sigma delta control unit includes an algorithm that cascades at least one first-order sigma delta to the TDC and extends a number of VCO cycles for the TDC to use in measuring the time difference.

2. The divider-less phase-locked loop system as recited in claim 1 , wherein the sigma delta control unit utilizes a (N−1) order sigma delta block, where N is an integer.

3. The divider-less phase-locked loop system as recited in claim 2 , wherein the (N−1) order sigma delta block facilitates a second order sigma delta loop response in the TDC.

4. The divider-less phase-locked loop system as recited in claim 1 , wherein operations of the VCO and the TDC is equivalent to a first order sigma delta.

5. The divider-less phase-locked loop system as recited in claim 1 , wherein the algorithm selects one edge of the VCO cycles for the TDC to use in measuring the time difference.

6. The divider-less phase-locked loop system as recited in claim 1 , wherein the TDC covers zero to two VCO cycles of the feedback signal for a second-order sigma delta.

7. The divider-less phase-locked loop system as recited in claim 1 , wherein the cascading facilitates a loop response that matches at least a second-order sigma delta.

8. The divider-less phase-locked loop system as recited in claim 1 further comprising a digital phase detector (DPD), wherein the DPD is configured to measure a frequency error at an output of the TDC.

9. A method of implementing a divider-less digital phase-locked loop (DPLL), the method comprising:
receiving of a reference signal and a feedback signal;
performing an algorithm that cascades a first-order sigma delta to a measurement and a digitization of a delay between the reference signal and the feedback signal; and
selecting an edge of the feedback signal by the algorithm, wherein the cascading extends a number of voltage controlled oscillator (VCO) cycles of the feedback signal in the measurement and the digitization of the delay.

10. The method as recited in claim 9 , wherein the cascading of the first-order sigma delta facilitates a second order sigma delta loop response.

11. The method as recited in claim 10 , wherein the edge is selected from a zero to two VCO cycles of the feedback signal for the second order sigma delta.

12. The method as recited in claim 9 , wherein the cascading of the first-order sigma delta facilitates a loop response that matches at least a second-order sigma delta.

13. A wireless device comprising: one or more processors; and
a transceiver coupled to the one or more processors, the transceiver further comprises:
a reference frequency oscillator configured to provide a reference signal;
a voltage controlled oscillator (VCO) configured to provide a feedback signal;
a time-to-digital converter (TDC) configured to receive the reference signal and the feedback signal; and
a sigma delta control unit that is coupled to the TDC, the sigma delta control unit includes an algorithm that cascades at least one first-order sigma delta to the TDC and extends a number of VCO cycles for the TDC to use in measuring the time difference.

14. The wireless device as recited in claim 13 , wherein the sigma delta control unit utilizes a (N−1) order sigma delta block, wherein N is an integer.

15. The wireless device as recited in claim 14 , wherein the (N−1) order sigma delta block facilitates a second order sigma delta loop response in the TDC.

16. The wireless device as recited in claim 13 , wherein operations of the VCO and the TDC is equivalent to a first order sigma delta.

17. The wireless device as recited in claim 13 wherein the algorithm selects one edge of the VCO cycles for the TDC to use in measuring the time difference.

18. The wireless device as recited in claim 13 , wherein the TDC covers zero to two VCO cycles of the feedback signal for a second-order sigma delta.

Assignees

• Intel Ip Corp

Inventors

• Banin Rotem
• Banin Elan
• Degani Ofir

Classifications

• H04B1/40

  Circuits · CPC title

• H03L2207/50

  All digital phase-locked loop · CPC title

• H03L7/16

  Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop · CPC title

• H03M7/3004

  Digital delta-sigma modulation · CPC title

• H03L7/085 Primary

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title