Cancellation of spurious tones within a phase-locked loop with a time-to-digital converter

Patent metadata

Field	Value
Publication number	US-9762250-B2
Application number	US-201414448458-A
Country	US
Kind code	B2
Filing date	Jul 31, 2014
Priority date	Nov 27, 2013
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A phase-locked loop (PLL) includes a spur cancellation circuit that receives a residue signal indicative of a first frequency and receives a residual phase error signal and generates a spur cancellation signal. A summing circuit combines the spur cancellation signal and a first phase error signal corresponding to a phase difference between a reference signal and a feedback signal in the PLL and generates a second phase error signal with a reduced spurious tone at the first frequency.

First claim

What is claimed is:

1. A phase-locked loop (PLL) comprising:
a spur cancellation circuit coupled to receive a residue signal indicative of a first spur frequency and to receive a residual phase error signal and to generate a spur cancellation signal; and
a circuit to combine the spur cancellation signal and a first phase error signal corresponding to a time difference between a reference signal and a feedback signal in the PLL and to generate a second phase error signal with a reduced spurious tone at the first spur frequency.

2. The PLL as recited in claim 1 wherein the residual phase error signal and the second phase error signal are the same signal.

3. The PLL as recited in claim 1 wherein the residual phase error signal has at least one additional spurious tone reduced compared to the second phase error signal.

4. The PLL as recited in claim 1 further comprising a delta sigma modulator coupled to receive a divide value for a feedback divider of the PLL and to supply the residue signal.

5. The PLL as recited in claim 1 further comprising an accumulator circuit to supply the residue signal.

6. The PLL as recited in claim 1 wherein the residue signal is a ramp signal that wraps in response to exceeding a predetermined value.

7. The PLL as recited in claim 1 further comprising:
a cosine generator coupled to the residue signal to supply a cosine sequence;
a sine generator coupled to the residue signal to supply a sine sequence;
a first multiplier coupled to multiply a delayed cosine sequence with the residual phase error signal and supply a first multiplier output;
a second multiplier coupled to multiply a delayed sine sequence with the residual phase error signal and supply a second multiplier output;
a first accumulate and dump circuit coupled to receive the first multiplier output and to accumulate the first multiplier output over a predetermined number of cycles of the spur cancellation signal and supply a first accumulate and dump output;
a second accumulate and dump circuit coupled to receive the second multiplier output and to accumulate the second multiplier output over the predetermined number of cycles of the spur cancellation signal and supply a second accumulate and dump output;
a first accumulator circuit coupled to the first accumulate and dump output and configured to supply a first scale factor;
a second accumulator circuit coupled to the second accumulate and dump output and configured to supply a second scale factor;
a third multiplier coupled to multiply the cosine sequence and the first scale factor and supply a scaled cosine sequence;
a fourth multiplier coupled to multiply the sine sequence and the second scale factor and supply a scaled sine sequence; and
a summing circuit to sum the scaled cosine sequence and the scaled sine sequence to generate the spur cancellation signal.

8. The PLL as recited in claim 7 further comprising:
a phase adjust circuit to generate combined weighted versions of the first and second accumulate and dump outputs and supply respective ones of the combined weighted versions to the first and second accumulator circuits.

9. The PLL as recited in claim 1 wherein the spur cancellation signal includes a sine component having a first scale factor and a cosine component having a second scale factor, the first and second scale factors being determined over M cycles of the spur cancellation signal, where M is a positive number, M being set initially to a first number of cycles and M being set during steady state operation to a second number of cycles equal to or larger than the first number of cycles.

10. The PLL as recited in claim 1 further comprising a second spur cancellation circuit coupled to generate a second spur cancellation signal to cancel a spurious tone at a second spur frequency, wherein the second spur cancellation circuit is coupled to receive a second residue signal corresponding to the second spur frequency.

11. The PLL as recited in claim 10 further comprising an accumulator circuit to supply the second residue signal as an input to the second spur cancellation circuit, the accumulator circuit configured to supply a sequence Φ norm [k]=Φ norm [k]+f spur T, where T is a sample period of the accumulator circuit, f spur is the second spur frequency, and the accumulator circuit wraps whenever it exceeds a predetermined value.

12. The PLL as recited in claim 10 wherein the second residue signal and the residue signal are the same signal and the second spur frequency is a harmonic of the first spur frequency.

13. The PLL as recited in claim 1
wherein the first spur frequency indicated by the residue signal is a frequency of a spurious tone at the first spur frequency caused by a fractional divide value in the PLL.

14. The PLL as recited in claim 1 wherein the first spur frequency indicated by the residue signal is a spur frequency of a non-fractional spur.

15. The PLL as recited in claim 1 further comprising:
a selector circuit coupled to receive a plurality of residue signals indicative of respective frequencies and supply a selected one of the residue signals as the residue signal indicative of the first spur frequency.

16. A method in a phase-locked loop (PLL) comprising:
receiving a residue signal corresponding to a first spur frequency at a spur cancellation circuit;
generating a spur cancellation signal for the first spur frequency using the residue signal and a residual phase error signal; and
subtracting the spur cancellation signal from a first phase error signal corresponding to a time difference between a reference signal and a feedback signal in the PLL, to generate a second phase error signal with a reduced spurious tone at the first spur frequency.

17. The method as recited in claim 16 wherein the residual phase error signal and the second phase error signal are the same signal.

18. The method as recited in claim 16 wherein the residual phase error signal has at least one additional spurious tone reduced compared to the second phase error signal.

19. The method as recited in claim 16 further comprising supplying the residue signal from a delta sigma modulator controlling a feedback divider in the PLL.

20. The method as recited in claim 16 further comprising supplying the residue signal from an accumulator circuit configured to generate the residue signal Φ norm [k]=Φ norm [k]+f spur T, where T is a sample period of the accumulator circuit, f spur is a frequency of interest for spur cancellation.

21. The method as recited in claim 16 further comprising:
generating sine and cosine sequences based on the residue signal;
correlating the sine and cosine sequences with the second phase error signal with the reduced spurious tone and supplying correlated sine and cosine sequences;
combining weighted versions of the correlated sine and cosine sequences and generating first and second weighted signals and accumulating the first and second weighted signals to generate first and second accumulated signals;
scaling the sine and cosine sequences using scale factors based respectively on the first and second accumulated signals and supplying scaled sine and cosine sequences; and
combining the scaled sine and cosine sequences to form the spur cancellation signal.

22. The method as recited in claim 21 further comprising correlating the sine and cosine sequences using delay circuits and multipliers and accumulate and dump circuits.

23. The method as recited

Assignees

• Silicon Lab Inc

Inventors

• Perrott Michael H

Classifications

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/0836

  of phase error, e.g. jitter · CPC title

• H03L7/0995

  the oscillator comprising a ring oscillator · CPC title

• H03M3/358

  of non-linear distortion, e.g. instability (avoiding instability by structural design H03M3/44) · CPC title