Semiconductor module

US11040872B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11040872-B2
Application numberUS-201916595532-A
CountryUS
Kind codeB2
Filing dateOct 8, 2019
Priority dateJul 20, 2016
Publication dateJun 22, 2021
Grant dateJun 22, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The method comprises fabricating a semiconductor panel comprising a plurality of semiconductor devices, fabricating a cap panel comprising a plurality of caps, bonding the cap panel onto the semiconductor panel so that each one of the caps covers one or more of the semiconductor devices, and singulating the bonded panels into a plurality of semiconductor modules.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor module comprising: a semiconductor device comprising a semiconductor body embedded within a first mold compound that defines molded sidewalls that surround an inner space, the semiconductor body including semiconductor sidewalls and a membrane connected across a lower edge of the semiconductor sidewalls; and a cap having an inner horizontal wall and inner side walls that adjoin the inner horizontal wall to define a cavity, the cap connected to the molded sidewalls of the semiconductor body and extending across a top of the inner space, the cap including an electrically conductive material to electrically shield the semiconductor device. 2. The semiconductor module of claim 1 , the cap comprising a mold compound, wherein the inner horizontal wall and the inner sidewalls of the cap form an upper surface of the inner space and are covered with a layer of electrically conductive material. 3. The semiconductor module of claim 1 , where the cap is formed from an electrically conductive material. 4. The semiconductor module of claim 1 , the semiconductor device comprising a microphone with the membrane comprising a microphone membrane such that the inner space forms a back volume of the microphone. 5. The semiconductor module of claim 4 , the cap having a thickness (c) between an upper surface of the cap and the inner horizontal wall of the cap, the cavity having a height (b) between the inner horizontal wall of the cap and a boundary between the cap and the molded sidewalls, the cap having a height (a) between the upper surface of the cap and the boundary between the cap and the molded sidewalls, wherein the height (a) is equal to a sum of the height (b) and the thickness (c), wherein for a same height (a) of the cap, a smaller thickness (c) of the cap will result in a greater height (b) of the cavity and a greater volume of the back volume and a greater signal-to-noise ratio of the microphone. 6. The semiconductor module of claim 1 , the semiconductor device comprising a sensor, the sensor comprising one of a pressure sensor, a shock sensor, an acceleration sensor, a temperature sensor, a gas sensor, a humidity sensor, a magnetic field sensor, an electric field sensor, and an optical sensor. 7. A microphone package comprising: sidewalls surrounding an inner space; a semiconductor body comprising a microphone membrane connected between the sidewalls to define a lower surface of the inner space; and a cap having an inner horizontal wall and inner side walls that adjoin the inner horizontal wall to define a cavity, the cap connected across upper surfaces of the sidewalls that surround the inner space to define an upper surface of the inner space, the inner space representing a back volume of the microphone membrane. 8. The microphone package of claim 7 , wherein the cap comprises a molding compound, wherein the inner horizontal wall and the inner side walls of the cap define the upper surface of the inner space which includes a layer of electrically conductive material to electrically shield the semiconductor body. 9. The microphone package of claim 7 , the cap comprising an electrically conductive material to electrically shield the semiconductor body. 10. The microphone package of claim 7 , the cap having a thickness (c) between an upper surface of the cap and the inner horizontal wall of the cap, the cavity having a height (b) between the inner horizontal wall of the cap and a boundary between the cap and the molded sidewalls, the cap having a height (a) between the upper surface of the cap and the boundary between the cap and the upper surfaces of the sidewalls, wherein the height (a) is equal to a sum of the height (b) and the thickness (c), wherein for a same height (a) of the cap, a smaller thickness (c) of the cap will result in a greater height (b) of the cavity and a greater volume of the back volume and a greater signal-to-noise ratio of the microphone package. 11. The microphone package of claim 7 , wherein the semiconductor body includes the sidewalls such that the microphone membrane is connected between the semiconductor body sidewalls and the cap is connected across upper surfaces of the semiconductor side walls. 12. The microphone package of claim 7 , wherein the semiconductor body includes the sidewalls, the microphone package further including mold walls of a molding compound surround the semiconductor body, wherein the cap is connected across upper surfaces of the mold walls. 13. The microphone package of claim 7 , wherein the sidewalls comprise a molding compound separate from the semiconductor body. 14. A microphone package comprising: a semiconductor body of a semiconductor material including: semiconductor sidewalls; and a microphone membrane connected across a lower edge of the semiconductor sidewalls, wherein the semiconductor sidewalls and the microphone membrane define an inner space between the semiconductor sidewalls; a mold compound surrounding outer faces of the semiconductor sidewalls to form molded sidewalls; and a cap having an inner horizontal wall and inner side walls that adjoin the inner horizontal wall to define a cavity, the cap connected across upper surfaces of the molded sidewalls to form an upper surface of the inner space, the inner space forming a back volume of the microphone membrane. 15. The microphone package of claim 14 , the cap having a thickness (c) between an upper surface of the cap and the inner horizontal wall of the cap, the cavity having a height (b) between the inner horizontal wall of the cap and a boundary between the cap and the molded sidewalls, the cap having a height (a) between the upper surface of the cap and the boundary between the cap and the upper surfaces of the molded sidewalls, wherein the height (a) is equal to a sum of the height (b) and the thickness (c), wherein for a same height (a) of the cap, a smaller thickness (c) of the cap will result in a greater height (b) of the cavity and a greater volume of the back volume and a greater signal-to-noise ratio of the microphone package. 16. The microphone package of claim 14 , wherein the cap comprises a mold compound and a metal layer on a surface of the inner horizontal wall and the inner side walls of the cap that form the upper surface of the inner space, the metal layer to provide electrical shielding for the semiconductor body. 17. The microphone package of claim 14 , including electrical contacts disposed on a bottom surface of the microphone package across a junction between the semiconductor sidewalls and the molded sidewalls.

Assignees

Inventors

Classifications

  • Microphones or microspeakers · CPC title

  • through the substrate · CPC title

  • Bonding of solid lids or wafers to the substrate · CPC title

  • for protecting against electromagnetic or electrostatic interferences · CPC title

  • the micromechanical device and the control or processing electronics being separate parts in the same package · CPC title

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Frequently asked questions

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What does patent US11040872B2 cover?
The method comprises fabricating a semiconductor panel comprising a plurality of semiconductor devices, fabricating a cap panel comprising a plurality of caps, bonding the cap panel onto the semiconductor panel so that each one of the caps covers one or more of the semiconductor devices, and singulating the bonded panels into a plurality of semiconductor modules.
Who is the assignee on this patent?
Infineon Technologies Ag
What technology area does this patent fall under?
Primary CPC classification B81C1/00269. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Jun 22 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).