Patterning material film stack with metal-containing top coat for enhanced sensitivity in extreme ultraviolet (EUV) lithography

Patent metadata

Field	Value
Publication number	US-11037786-B2
Application number	US-201916404404-A
Country	US
Kind code	B2
Filing date	May 6, 2019
Priority date	Dec 19, 2017
Publication date	Jun 15, 2021
Grant date	Jun 15, 2021

Abstract

A semiconductor structure includes a semiconductor substrate and a multi-layer patterning material film stack formed on the semiconductor substrate. The patterning material film stack includes a resist layer formed over one or more additional layers. The semiconductor structure further includes a metal-containing top coat formed over the resist layer. The metal-containing top coat can be formed, for example, by atomic layer deposition or spin-on deposition over the resist layer, or by self-segregation from the resist layer.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a semiconductor substrate; and
a resist mixture comprising a resist material and a metal additive, the resist material configured to form a resist layer of a multi-layer patterning material film stack disposed on the semiconductor substrate, the patterning material film stack comprising the resist layer disposed over one or more additional layers, the metal additive adapted to self-segregate to thereby configure a metal-containing top coat disposed over the resist layer.

2. The semiconductor structure of claim 1 wherein the metal-containing top coat comprises at least one of a transition metal and a post-transition metal.

3. The semiconductor structure of claim 1 wherein the metal-containing top coat comprises a metal oxide.

4. The semiconductor structure of claim 1 wherein the metal-containing top coat is soluble in a developer solution used in developing a pattern formed in the resist layer.

5. The semiconductor structure of claim 1 wherein the metal additives are configured and adapted to self-segregate from the resist material when subjected to a designated treatment process.

6. The semiconductor structure of claim 1 wherein the designated treatment process includes a bake process.

7. The semiconductor structure of claim 1 including one or more additional layers of the metal-containing top coat.

8. The semiconductor structure of claim 1 wherein the metal-containing top coat comprises properties enabling solubility in a developer solution used in developing a pattern formed in the resist layer.

9. A metal-containing material configured to form a metal-containing top coat over a resist layer of a multi-layer patterning material film stack disposed on a semiconductor substrate, the patterning material film stack comprising the resist layer and one or more additional layers over which the resist layer is disposed, the metal-containing material comprising metal additives disposed within a resist mixture comprising a resist material and the metal additives, the metal additives being configured and having properties to self-segregate from the resist mixture such that the metal-containing top coat is disposed over the resist layer.

10. The metal-containing material of claim 9 wherein the metal-containing material comprises at least one of a transition metal and a post-transition metal.

11. The metal-containing material of claim 9 wherein the metal-containing material comprises a metal oxide.

12. The metal-containing material of claim 9 wherein the metal-containing material comprises a self-segregating fluorine functionalized metal additive.

13. The metal-containing material of claim 9 wherein the metal additives are configured and adapted to self-segregate from the resist material when subjected to a designated treatment process.

14. The metal-containing material of claim 9 wherein the designated treatment process includes a bake process.

15. The metal-containing material of claim 9 including one or more additional layers of the metal-containing top coat.

16. The metal-containing material of claim 9 wherein the metal-containing top coat comprises properties enabling solubility in a developer solution used in developing a pattern formed in the resist layer.

Assignees

• IBM

Inventors

• De Silva Ekmini Anuja
• Goldfarb Dario
• Felix Nelson
• Corliss Daniel
• Wojtecki Rudy J

Classifications

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/4083

  characterised by their behaviours during the lithography processes, e.g. soluble masks or redeposited masks · CPC title

• H10P76/204

  of organic photoresist masks · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title