Local trap-rich isolation

Patent metadata

Field	Value
Publication number	US-2018096884-A1
Application number	US-201615281418-A
Country	US
Kind code	A1
Filing date	Sep 30, 2016
Priority date	Sep 30, 2016
Publication date	Apr 5, 2018
Grant date	—

Abstract

A trap-rich polysilicon layer is interposed between the active (SOI) layer and the underlying handle portion of a semiconductor substrate to prevent or minimize parasitic surface conduction effects within the active layer and promote device linearity. In various embodiments, the trap-rich layer extends vertically through a portion of an isolation layer and laterally therefrom between the isolation layer and the handle portion of the substrate to underlie a portion of the device active area.

First claim

1 . A method of manufacturing a semiconductor device, comprising:
forming an isolation trench through a first semiconductor layer of a semiconductor substrate and partially through an isolation layer underlying the first semiconductor layer; forming spacers on sidewalls of the isolation trench; forming a lateral cavity within the isolation layer extending from the isolation trench between a portion of the isolation layer and a second semiconductor layer underlying the isolation layer; forming a polysilicon layer within the isolation trench and the lateral cavity; forming a gate oxide layer over the first semiconductor layer and overlying the polysilicon layer within the lateral cavity: forming a polysilicon gate over the gate oxide layer; forming a dielectric layer over the polysilicon gate; etching a contact via through the dielectric layer; and forming a contact within the contact via in electrical communication with the polysilicon gate, wherein a portion of the first semiconductor layer overlying the polysilicon layer within the lateral cavity comprises an active layer of a switch field effect transistor.

2 . The method of claim 1 , wherein forming the isolation trench comprises etching through at least 50% of a thickness of the isolation layer.

3 . The method of claim 1 , wherein the isolation trench is formed peripheral to a portion of the first semiconductor layer.

4 . The method of claim 1 , wherein the lateral cavity underlies a portion of the first semiconductor layer.

5 . The method of claim 1 , wherein forming the lateral cavity comprises selectively etching the isolation layer with respect to the spacers, the first semiconductor layer, and the second semiconductor layer.

6 . The method of claim 1 , wherein the polysilicon layer fills the isolation trench and the lateral cavity.

7 . The method of claim 1 , wherein the polysilicon layer is formed directly over the second semiconductor layer.

8 . The method of claim 1 , wherein the polysilicon layer is formed peripheral to and below a portion of the first semiconductor layer.

9 . The method of claim 1 , further comprising implanting a dopant into the first semiconductor layer to form an active region.

10 . The method of claim 1 , further comprising etching the polysilicon layer below a top surface of the isolation layer within the isolation trench.

11 . The method of claim 10 , further comprising forming a dielectric layer on the polysilicon layer within the isolation trench.

12 . (canceled)

13 . A semiconductor device, comprising:
a doped semiconductor layer disposed over an isolation layer of a semiconductor substrate; and a polysilicon layer embedded within the isolation layer, the polysilicon layer peripheral to and partially underlying the doped semiconductor layer.

14 . The semiconductor device of claim 13 , wherein the polysilicon layer comprises trap-rich polysilicon.

15 . The semiconductor device of claim 13 , wherein the polysilicon layer is substantially free of voids.

16 . The semiconductor device of claim 13 , wherein a recessed top surface of the polysilicon layer is below a top surface of the isolation layer.

17 . The semiconductor device of claim 16 , further comprising a dielectric layer disposed on the recessed top surface.

18 . The semiconductor device of claim 16 , further comprising a silicide layer disposed on the recessed top surface.

19 . The semiconductor device of claim 13 , wherein the isolation layer overlies a handle portion of the semiconductor substrate.

20 . The semiconductor device of claim 13 , wherein the doped semiconductor layer comprises an active layer of a switch FET.

Assignees

• Globalfoundries Inc

Inventors

• Shank Steven M
• Abou-Khalil Michel

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title

• H10W10/041

  of isolation regions comprising polycrystalline semiconductor materials · CPC title