Self-aligned lithographic patterning with variable spacings

Patent metadata

Field	Value
Publication number	US-9711447-B1
Application number	US-201615290277-A
Country	US
Kind code	B1
Filing date	Oct 11, 2016
Priority date	Oct 11, 2016
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

Methods of lithographic patterning and structures formed by lithographic patterning. A hardmask layer is formed on a dielectric layer, a feature is formed on the hardmask layer, and a mandrel is formed that extends in a first direction across the first feature. The mandrel and the hardmask layer beneath the mandrel are removed to pattern the hardmask layer with the feature masking a section of the hardmask layer. After the hardmask layer is patterned, the dielectric layer is etched to form a first trench and a second trench that are separated by a section of the dielectric layer masked by the section of the hardmask layer. The first trench and the second trench are filled with a conductor layer to respectively form a first wire and a second wire that is separated from the first wire by the section of the dielectric layer.

First claim

What is claimed is:

1. A method comprising:
forming a hardmask layer on a dielectric layer;
forming a first feature on the hardmask layer;
forming a first mandrel that extends in a first direction across the first feature;
removing the first mandrel and the hardmask layer beneath the first mandrel to pattern the hardmask layer with the first feature masking a first section of the hardmask layer;
after the hardmask layer is patterned, etching the dielectric layer to form a first trench and a second trench separated by a section of the dielectric layer masked by the first section of the hardmask layer; and
filling the first trench and the second trench with a conductor layer to respectively form a first wire and a second wire separated from the first wire by the section of the dielectric layer.

2. The method of claim 1 further comprising:
forming a sidewall spacer on the first mandrel,
wherein the sidewall spacer extends in the first direction across the first feature.

3. The method of claim 2 wherein a portion of the first feature is located peripherally outside of the sidewall spacer in a second direction perpendicular to the first direction, and further comprising:
removing the portion of the first feature before the hardmask layer is patterned.

4. The method of claim 2 wherein the sidewall spacer is formed on the first mandrel before the dielectric layer is etched to form the first trench and the second trench.

5. The method of claim 2 wherein the first wire and the second wire have a tip-to-tip spacing based on a length of the first feature in the first direction.

6. The method of claim 5 wherein the length of the first feature is independent of a thickness of the sidewall spacer.

7. The method of claim 2 wherein the first feature has a dimension in the first direction parallel to a length of the first mandrel that is greater than twice a thickness of the sidewall spacer.

8. The method of claim 2 wherein the sidewall spacer masks the hardmask layer against removal when the first mandrel and the hardmask layer beneath the first mandrel are removed, and a second section of the hardmask layer beneath the sidewall spacer provides a boundary for the first trench and the second trench in a second direction perpendicular to the first direction after the hardmask layer is patterned.

9. The method of claim 2 wherein a second section of the hardmask layer beneath the sidewall spacer is masked when the hardmask layer is patterned.

10. The method of claim 1 wherein forming the first feature on the hardmask layer comprises:
depositing a first layer on the hardmask layer;
patterning the first layer to form the first feature; and
after the first feature is formed, depositing a second layer in which the first feature is embedded.

11. The method of claim 10 further comprising:
before the hardmask layer is patterned, removing the second layer selective to the first feature,
wherein the hardmask layer is exposed for removal during patterning where the second layer is removed.

12. The method of claim 1 wherein forming the first feature on the hardmask layer comprises:
depositing a first layer on the hardmask layer:
patterning the first layer to form an opening; and
after the opening is formed, depositing a second layer that fills the opening to form the first feature.

13. The method of claim 12 further comprising:
before the hardmask layer is patterned, removing the first layer selective to the second layer,
wherein the hardmask layer is exposed for removal during patterning where the first layer is removed.

14. The method of claim 1 further comprising:
forming a second feature on the hardmask layer;
wherein a third trench is formed between the first trench and the second feature when the dielectric layer is etched, and a third wire is formed by a portion of the conductor layer filling in the third trench.

15. The method of claim 14 further comprising:
before the dielectric layer is etched, forming a second mandrel that extends in the first direction across the second feature; and
removing the second mandrel and the hardmask layer beneath the second mandrel to pattern the hardmask layer with the second feature masking a second section of the hardmask layer,
wherein the third trench is formed laterally between the first section of the hardmask layer and the second section of the hardmask layer.

16. The method of claim 1 further comprising:
after the dielectric layer is etched to form the first trench and the second trench, removing the first feature before the first trench and the second trench are filled with the conductor layer to respectively form the first wire and the second wire.

17. A structure comprising:
a first wire having a first tip and a side edge that terminates at the first tip;
a second wire having a second tip separated in a first direction from the first tip by a gap; and
a dielectric layer including a strip adjacent to the side edge of the first wire and a section located in the gap between the first tip of the first wire and the second tip of the second wire, the section of the dielectric layer having a length in the first direction, and the strip having a width extending in a second direction perpendicular to the first direction,
wherein the length of the section of the dielectric layer is greater than the width of the strip.

18. The structure of claim 17 further comprising:
a third wire arranged in the first direction parallel with the first wire and the second wire,
wherein the strip of the dielectric layer is located laterally between the first wire and the third wire and is located laterally between the second wire and the third wire.

19. The structure of claim 17 wherein the first wire and the second wire are arranged in a row, the first wire has a width in the second direction, the second wire has a width in the second direction, and the width of the first wire is equal to the width of the second wire.

20. The structure of claim 19 wherein the section has a width in the second direction, the width of the section of the dielectric layer is greater than the width of the first wire, and the width of the section of the dielectric layer is greater than the width of the second wire.

Assignees

• Globalfoundries Inc

Inventors

• Shu Jiehui
• Fang Qiang
• Fisher Daniel W
• Huang Haigou
• Liu Jinping
• Sheng Haifeng
• Sun Zhiguo

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• H01L21/76877

  Electricity · mapped topic