Semiconductor device, method of manufacturing semiconductor device, and electronic apparatus

Patent metadata

Field	Value
Publication number	US-11031431-B2
Application number	US-201816497106-A
Country	US
Kind code	B2
Filing date	Feb 15, 2018
Priority date	Apr 4, 2017
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

A semiconductor device including a plurality of substrates that is stacked, each of the substrates including a semiconductor substrate and a multi-layered wiring layer stacked on the semiconductor substrate, the semiconductor substrate having a circuit with a predetermined function formed thereon. Bonding surfaces between two substrates among the plurality of substrates have an electrode junction structure in which electrodes formed on the respective bonding surfaces are joined in direct contact with each other, the electrode junction structure being a structure for electrical connection between the two substrates. One of the electrode constituting the electrode junction structure or a via for connection of the electrode to a wiring line in the multi-layered wiring layer is provided with a porous film, in a partial region between an electrically-conductive material and a sidewall of a through hole filled with the electrically-conductive material, the electrically-conductive material constituting the electrode and the via.

First claim

The invention claimed is:

1. A method of manufacturing a semiconductor device, comprising:
preparing a plurality of substrates, wherein
each of the plurality of substrates includes a semiconductor substrate and a multi-layered wiring layer stacked on the semiconductor substrate, and
the semiconductor substrate includes a circuit with a specific function; and

stacking the plurality of substrates, wherein
the plurality of substrates includes a plurality of bonding surfaces between at least two substrates of the plurality of substrates,
the plurality of bonding surfaces includes an electrode junction structure in which a plurality of electrodes on the plurality of bonding surfaces are joined in direct contact with each other,
the electrode junction structure is a structure for electrical connection between the two substrates, and
the plurality of electrodes and a via for connection of the plurality of electrodes to a wiring line in the multi-layered wiring layer includes:
forming a through hole that extends from one surface of a first substrate of the plurality of substrates to the wiring line,
forming a porous film including a porous material on at least a partial region of a sidewall of the through hole, and
filling the through hole having the porous film formed therein with an electrically-conductive material constituting the plurality of electrodes and the via.

2. The method of manufacturing the semiconductor device according to claim 1 , wherein
the electrode junction structure is formed by bonding the two substrates together in a state in which the plurality of electrodes formed on the plurality of bonding surfaces are in direct contact with each other,
performing heat treatment to join the plurality of electrodes in contact with each other.

3. The method of manufacturing the semiconductor device according to claim 2 , wherein the formation of the porous film includes steps of stacking a SiO2 film and a SiCN film in this order on at least the partial region of the sidewall of the through hole, and etching the SiO2 film by wet etching.

4. The method of manufacturing the semiconductor device according to claim 2 , wherein the formation of the porous film includes deposition of porous silica on at least the sidewall of the through hole by a chemical vapor deposition method.

5. A semiconductor device, comprising:
a stack of a plurality of substrates, wherein
each of the plurality of substrates includes a semiconductor substrate and a multi-layered wiring layer stacked on the semiconductor substrate, and
the semiconductor substrate includes a circuit with a specific function, and

a plurality of bonding surfaces between at least two substrates of the plurality of substrates, wherein
the plurality of bonding surfaces includes an electrode junction structure in which a plurality of electrodes on the plurality of bonding surfaces are joined in direct contact with each other,
the electrode junction structure is a structure for electrical connection between the two substrates,
the plurality of electrodes and a via for connection of the plurality of electrodes to a wiring line in the multi-layered wiring layer includes a porous film,
the porous film includes a porous material,
the porous film is in at least a partial region between an electrically-conductive material and a sidewall of a through hole filled with the electrically-conductive material, and
the electrically-conductive material constituting the plurality of electrodes and the via.

6. The semiconductor device according to claim 5 , wherein
the porous film is over an entire surface between the electrically-conductive material and the sidewall of the through hole filled with the electrically-conductive material, and
the electrically-conductive material constituting the plurality of electrodes and the via.

7. The semiconductor device according to claim 5 , wherein the via has a structure in which the through hole penetrating the semiconductor substrate is filled with the electrically-conductive material.

8. The semiconductor device according to claim 5 , wherein
a first substrate of the plurality of substrates is a pixel substrate including a pixel unit in which pixels are two-dimensionally arranged on the semiconductor substrate, and
the semiconductor device comprises a solid-state imaging device.

9. The semiconductor device according to claim 8 , wherein
a second substrate of the plurality of substrates is directly below the first substrate,
the first substrate includes a pixel signal-processing circuit that performs analog-to-digital conversion on a pixel signal acquired in each of the pixels, and
the electrode junction structure transmits the pixel signal to the pixel signal-processing circuit for each of the pixels.

10. The semiconductor device according to claim 5 , wherein the porous film is a SiO2 film made porous.

11. The semiconductor device according to claim 10 , wherein
the electrically-conductive material constituting the plurality of electrodes and the via is copper, and
an insulating material, a barrier metal, and the porous material are present between the copper and the sidewall of the through hole filled with the copper, in this order from the sidewall side.

12. The semiconductor device according to claim 10 , wherein
the electrically-conductive material constituting the plurality of electrodes and the via is copper, and
SiN, the porous material, SiCN, and a barrier metal are present between the copper and the sidewall of the through hole filled with the copper, in this order from the sidewall side.

13. The semiconductor device according to claim 10 , wherein
the electrically-conductive material constituting the plurality of electrodes and the via is copper, and
SiN and the porous material are present between the copper and the sidewall of the through hole filled with the copper, in this order from the sidewall side.

14. An electronic apparatus with a solid-state imaging device that electronically images an observation object, the solid-state imaging device, comprising:
a stack of a plurality of substrates, wherein
each of the plurality of substrates includes a semiconductor substrate and a multi-layered wiring layer stacked on the semiconductor substrate, and
the semiconductor substrate includes a circuit with a specific function,

a plurality of bonding surfaces between at least two substrates of the plurality of substrates, wherein
the plurality of bonding surfaces includes have an electrode junction structure in which a plurality of electrodes on the plurality of bonding surfaces are joined in direct contact with each other, and
the electrode junction structure is a structure for electrical connection between the two substrates,
the plurality of electrodes and a via for connection of the plurality of electrodes to a wiring line in the multi-layered wiring layer includes a porous film,
the porous film includes a porous material,
the porous film is in at least a partial region between an electrically-conductive material and a sidewall of a through hole filled with the electrically-conductive material, and
the electrically-conductive material constituting the plurality of electrodes and the via.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Fujii Nobutoshi
• Hagimoto Yoshiya

Classifications

• H10P50/283

  by chemical means · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W72/01935

  by plating, e.g. electroless plating or electroplating · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title