Semiconductor device and method of manufacturing the same semiconductor device

Patent metadata

Field	Value
Publication number	US-2016268163-A1
Application number	US-201615063187-A
Country	US
Kind code	A1
Filing date	Mar 7, 2016
Priority date	Mar 13, 2015
Publication date	Sep 15, 2016
Grant date	—

Abstract

The semiconductor device includes a semiconductor layer in which a via hole penetrating an upper surface of the semiconductor layer to a lower surface of the semiconductor layer is provided. The semiconductor device includes a first insulating film provided over the lower surface of the semiconductor layer and an inner surface of the via hole. The semiconductor device includes a second insulating film provided over the lower surface of the semiconductor layer and the inner surface of the via hole with the first insulating film interposed between the second insulating film and the semiconductor layer. The semiconductor device includes a device layer including a semiconductor element and provided on the side of the upper surface of the semiconductor layer.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a semiconductor layer in which a via hole penetrating an upper surface of the semiconductor layer to a lower surface of the semiconductor layer is provided; a first insulating film provided over the lower surface of the semiconductor layer and an inner surface of the via hole; a second insulating film provided over the lower surface of the semiconductor layer and the inner surface of the via hole with the first insulating film interposed between the second insulating film and the semiconductor layer; a device layer including a semiconductor element and provided on the side of the upper surface of the semiconductor layer; a lower electrode that is provided in the via hole with the first and second insulating films interposed between the lower electrode and the inner surface of the via hole and is electrically connected to the device layer; a protective insulating film that is provided on the upper surface of the semiconductor layer with the device layer interposed therebetween and protects the device layer; and an upper electrode that is provided to be opposed to the lower electrode with the device layer interposed therebetween and is electrically connected to the device layer.

2 . The semiconductor device according to claim 1 , wherein one of the first insulating film and the second insulating film has a greater coefficient of linear expansion than the semiconductor layer, and another of the first insulating film and the second insulating film has a smaller coefficient of linear expansion than the semiconductor layer.

3 . The semiconductor device according to claim 2 , wherein the first insulating film has a smaller coefficient of linear expansion than the semiconductor layer, and the second insulating film has a greater coefficient of linear expansion than the semiconductor layer.

4 . The semiconductor device according to claim 2 , wherein the one of the first insulating film and the second insulating film that has a greater coefficient of linear expansion than the semiconductor layer is a Low-k film.

5 . The semiconductor device according to claim 3 , wherein the second insulating film that has a greater coefficient of linear expansion than the semiconductor layer is a Low-k film.

6 . The semiconductor device according to claim 1 , wherein the semiconductor layer is a silicon layer.

7 . The semiconductor device according to claim 2 , wherein the semiconductor layer is a silicon layer.

8 . The semiconductor device according to claim. 3 , wherein the semiconductor layer is a silicon layer.

9 . The semiconductor device according to claim 2 , wherein the one of the first insulating film and the second insulating film that has a greater coefficient of linear expansion than the semiconductor layer has a lower step coverage than the another of the first insulating film and the second insulating film.

10 . The semiconductor device according to claim 7 , wherein the one of the first insulating film and the second insulating film that has a greater coefficient of linear expansion than the semiconductor layer has a lower step coverage than the another of the first insulating film and the second insulating film.

11 . A method of manufacturing a semiconductor device, comprising:
forming a device layer including a semiconductor element on a semiconductor layer; forming, on the device layer, a protective insulating film in which an opening part is provided; forming an upper electrode on the device layer in the opening part of the protective insulating film; shaving a part of the semiconductor layer at a lower surface side thereof to reduce the thickness of the semiconductor layer; forming a via hole that penetrates the semiconductor layer from an upper surface of the semiconductor layer to the lower surface of the semiconductor layer to expose a lower surface of the device layer; forming a first insulating film over the lower surface of the semiconductor layer and an inner surface of the via hole; forming a second insulating film over the lower surface of the semiconductor layer and the inner surface of the via hole with the first insulating film interposed between the second insulating film and the semiconductor layer; and forming a lower electrode electrically connected to the device layer in the via hole with the first insulating film and the second insulating film interposed between the lower electrode and the inner surface of the via hole.

12 . The method of manufacturing a semiconductor device according to claim 11 , further comprising:
selectively removing the first insulating film and the second insulating film over the lower surface of the device layer in the via hole.

13 . The method of manufacturing a semiconductor device according to claim 11 , wherein the upper electrode and the lower electrode are electrically connected to the device layer.

14 . The method of manufacturing a semiconductor device according to claim 12 , wherein the upper electrode and the lower electrode are electrically connected to the device layer.

15 . The method of manufacturing a semiconductor device according to claim 11 , wherein one of the first insulating film and the second insulating film has a greater coefficient of linear expansion than the semiconductor layer, and another of the first insulating film and the second insulating film has a smaller coefficient of linear expansion than the semiconductor layer.

16 . The method of manufacturing a semiconductor device according to claim 15 , wherein the first insulating film has a smaller coefficient of linear expansion than the semiconductor layer, and the second insulating film has a greater coefficient of linear expansion than the semiconductor layer.

17 . The method of manufacturing a semiconductor device according to claim 11 , wherein the semiconductor layer is a silicon layer.

18 . The method of manufacturing a semiconductor device according to claim 12 , wherein the semiconductor layer is a silicon layer.

19 . The method of manufacturing a semiconductor device according to claim 13 , wherein the semiconductor layer is a silicon layer.

20 . The method of manufacturing a semiconductor device according to claim 15 , wherein the one of the first insulating film and the second insulating film that has a greater coefficient of linear expansion than the semiconductor layer has a lower step coverage than the another of the first insulating film and the second insulating film.

Assignees

• Toshiba Kk

Inventors

• Nakamura Kenro

Classifications

• H10W20/0265

  characterised by the sidewall insulation · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title

• H10W20/076

  in via holes or trenches · CPC title