Switched-capacitor DC-to-DC converters and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-9853541-B2
Application number	US-201715584923-A
Country	US
Kind code	B2
Filing date	May 2, 2017
Priority date	Jul 13, 2015
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A switched-capacitor DC-to-DC converter includes a logic cell and a capacitor cell vertically overlapping with the logic cell. The logic cell has a plurality of active elements disposed over a first substrate. The capacitor cell has a capacitor over a second substrate. A first interlayer insulation layer disposed over the first substrate is bonded to a second interlayer insulation layer disposed over the second substrate. A first through via connected to any one of interconnection patterns of the logic cell and a second through via connected to a lower electrode pattern of the capacitor cell are connected to each other through a first external circuit pattern. A third through via connected to an upper electrode pattern of the capacitor cell and a fourth through via connected to another one of the interconnection patterns of the logic cell are connected to each other through a second external circuit pattern.

First claim

What is claimed is:

1. A switched-capacitor DC-to-DC converter comprising:
a logic cell having (i) a first substrate, (ii) a plurality of active elements disposed over the first substrate, (iii) a first interlayer insulation layer disposed over a top surface of the first substrate to cover the active elements, and (iv) a plurality of interconnection patterns disposed in the first interlayer insulation layer and electrically connected to the active elements, wherein the plurality of interconnection patterns include first and second interconnection patterns;
a capacitor cell having (i) a second substrate, (ii) a capacitor disposed over a top surface of the second substrate, (iii) a second interlayer insulation layer disposed over the second substrate to cover the capacitor, (iv) a lower interconnection pattern disposed in the second interlayer insulation layer and electrically connected to a lower electrode pattern of the capacitor, and (v) an upper interconnection pattern disposed in the second interlayer insulation layer and electrically connected to an upper electrode pattern of the capacitor, wherein the second substrate is bonded to the first interlayer insulation layer so that the logic cell vertically overlaps with the capacitor cell;
a first through via penetrating the second interlayer insulation layer and the second substrate and extending into the first interlayer insulation layer to contact the first interconnection pattern;
a second through via disposed in the second interlayer insulation layer to contact the lower interconnection pattern;
a third through via disposed in the second interlayer insulation layer to contact the upper interconnection pattern;
a fourth through via penetrating the second interlayer insulation layer and the second substrate and extending into the first interlayer insulation layer to contact the second interconnection pattern;
a first external circuit pattern disposed over a top surface of the second interlayer insulation layer opposite to the second substrate and electrically connected to the first and second through vias; and
a second external circuit pattern disposed over the top surface of the second interlayer insulation layer and electrically connected to the third and fourth through vias wherein the first substrate and the first interlayer insulation layer are in direct contact with each other.

2. The switched-capacitor DC-to-DC converter of claim 1 ,
wherein the plurality of active elements includes first and second CMOS devices,
wherein the first CMOS device includes a first P-channel MOS transistor and a first N-channel MOS transistor, and
wherein the second CMOS device includes a second P-channel MOS transistor and a second N-channel MOS transistor.

3. The switched-capacitor DC-to-DC converter of claim 2 ,
wherein the first interconnection pattern is electrically connected to a drain region of the first P-channel MOS transistor and a drain region of the first N-channel MOS transistor, and
wherein the second interconnection pattern is electrically connected to a drain region of the second P-channel MOS transistor and a drain region of the second N-channel MOS transistor.

4. The switched-capacitor DC-to-DC converter of claim 3 ,
wherein the first interconnection pattern is electrically connected to the first through via, and
wherein the second interconnection pattern is electrically connected to the fourth through via.

5. The switched-capacitor DC-to-DC converter of claim 1 , wherein the lower interconnection pattern is disposed over the top surface of the second substrate opposite to the first interlayer insulation layer.

6. The switched-capacitor DC-to-DC converter of claim 5 , further comprising:
a dummy insulation pattern disposed over the lower interconnection pattern,
wherein a plurality of contact holes are formed in the dummy insulation pattern.

7. The switched-capacitor DC-to-DC converter of claim 6 , wherein the lower interconnection pattern is exposed by the contact holes, wherein tire capacitor includes: the lower electrode pattern disposed over the dummy insulation pattern; a dielectric pattern disposed over the lower electrode pattern; and the upper electrode pattern disposed over the dielectric pattern, and wherein the capacitor the contact holes.

8. The switched-capacitor DC-to-DC converter of claim 7 ,
wherein a top surface of the upper electrode pattern opposite to the dummy insulation pattern and is in direct contact with a bottom surface of the upper interconnection pattern.

9. The switched-capacitor DC-to-DC converter of claim 1 ,
wherein each of the first and second substrates is a silicon layer.

Assignees

• Sk Hynix Inc

Inventors

• Hwang Jae Ho

Classifications

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/43

  Layouts of interconnections · CPC title