Solid-state imaging device and electronic apparatus

Patent metadata

Field	Value
Publication number	US-2020105813-A1
Application number	US-201816497497-A
Country	US
Kind code	A1
Filing date	Mar 23, 2018
Priority date	Apr 4, 2017
Publication date	Apr 2, 2020
Grant date	—

Abstract

[Object] To provide a solid-state imaging device and an electronic apparatus with further improved performance. [Solution] A solid-state imaging device including: a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked; a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked; and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. The pixel unit has pixels arranged thereon. The first substrate and the second substrate are bonded together in a manner that the first multi-layered wiring layer and the second semiconductor substrate are opposed to each other. A first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate to each other does not include a coupling structure formed from the first substrate as a base over bonding surfaces of the first substrate and the second substrate. Alternatively, the first coupling structure does not exist.

First claim

1 . A solid-state imaging device comprising:
a first substrate including a first semiconductor substrate and a first multi-layered wiring layer stacked on the first semiconductor substrate, the first semiconductor substrate having a pixel unit formed thereon, the pixel unit having pixels arranged thereon; a second substrate including a second semiconductor substrate and a second multi-layered wiring layer stacked on the second semiconductor substrate, the second semiconductor substrate having a circuit formed thereon, the circuit having a predetermined function; and a third substrate including a third semiconductor substrate and a third multi-layered wiring layer stacked on the third semiconductor substrate, the third semiconductor substrate having a circuit formed thereon, the circuit having a predetermined function, the first substrate, the second substrate, and the third substrate being stacked in this order, the first substrate and the second substrate being bonded together in a manner that the first multi-layered wiring layer and the second semiconductor substrate are opposed to each other, a first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate to each other not existing, or not including a coupling structure formed from the first substrate as a base over bonding surfaces of the first substrate and the second substrate.

2 . The solid-state imaging device according to claim 1 , wherein the first coupling structure includes an opening provided from a back surface side of the first substrate to expose a predetermined wiring line in the first multi-layered wiring layer, and an opening provided by penetrating at least the first substrate from the back surface side of the first substrate to expose a predetermined wiring line in the second multi-layered wiring layer.

3 . The solid-state imaging device according to claim 2 , further comprising a second coupling structure for electrically coupling the circuit of the second substrate and the circuit of the third substrate to each other, wherein
the second coupling structure includes an opening provided by penetrating at least the first substrate from a back surface side of the second substrate to expose a predetermined wiring line in the second multi-layered wiring layer, and an opening provided by penetrating at least the first substrate and the second substrate from the back surface side of the first substrate to expose a predetermined wiring line in the third multi-layered wiring layer.

4 . The solid-state imaging device according to claim 3 , wherein the predetermined wiring line in the second multi-layered wiring layer that is exposed by the opening and the predetermined wiring line in the third multi-layered wiring layer that is exposed by the opening comprise pads that function as I/O units.

5 . The solid-state imaging device according to claim 3 , wherein
pads that function as I/O units exist on a back surface of the first substrate, a film including an electrically-conductive material is formed on an inner wall of the opening, and the predetermined wiring line in the second multi-layered wiring layer that is exposed by the opening and the predetermined wiring line in the third multi-layered wiring layer that is exposed by the opening are electrically coupled to the pads by the electrically-conductive material.

6 . The solid-state imaging device according to claim 5 , wherein the predetermined wiring line in the second multi-layered wiring layer and the predetermined wiring line in the third multi-layered wiring layer are electrically coupled to the same pad by the electrically-conductive material.

7 . The solid-state imaging device according to claim 5 , wherein the predetermined wiring line in the second multi-layered wiring layer and the predetermined wiring line in the third multi-layered wiring layer are electrically coupled to the pads by the electrically-conductive material, the pads being different from each other.

8 . The solid-state imaging device according to claim 1 , further comprising a second coupling structure for electrically coupling the circuit of the second substrate and the circuit of the third substrate to each other, wherein
the second substrate and the third substrate are bonded together in a manner that the second multi-layered wiring layer and the third multi-layered wiring layer are opposed to each other, and the second coupling structure includes a via provided by penetrating the second substrate or the third substrate, the via electrically coupling a predetermined wiring line in the second multi-layered wiring layer and a predetermined wiring line in the third multi-layered wiring layer to each other.

9 . The solid-state imaging device according to claim 8 , wherein the via has a structure in which electrically-conductive materials are embedded in a first through hole that exposes the predetermined wiring line in the second multi-layered wiring layer and a second through hole that exposes the predetermined wiring line in the third multi-layered wiring layer and is different from the first through hole, or a structure in which films including electrically-conductive materials are formed on inner walls of the first through hole and the second through hole.

10 . The solid-state imaging device according to claim 8 , wherein the via has a structure in which an electrically-conductive material is embedded in one through hole provided to contact the predetermined wiring line in the second multi-layered wiring layer and expose the predetermined wiring line in the third multi-layered wiring layer, or one through hole provided to contact the predetermined wiring line in the third multi-layered wiring layer and expose the predetermined wiring line in the second multi-layered wiring layer, or a structure in which a film including an electrically-conductive material is formed on an inner wall of the one through hole.

11 . The solid-state imaging device according to claim 1 , further comprising a third coupling structure for electrically coupling the circuit of the first substrate and the circuit of the third substrate to each other, wherein
the second substrate and the third substrate are bonded together in a manner that the second multi-layered wiring layer and the third multi-layered wiring layer are opposed to each other, and the third coupling structure includes a via provided by penetrating at least the second substrate from the back surface side of the first substrate or a back surface side of the third substrate, the via electrically coupling a predetermined wiring line in the first multi-layered wiring layer and a predetermined wiring line in the third multi-layered wiring layer to each other.

12 . The solid-state imaging device according to claim 11 , wherein the via has a structure in which electrically-conductive materials are embedded in a first through hole that exposes the predetermined wiring line in the first multi-layered wiring layer, and a second through hole that exposes the predetermined wiring line in the third multi-layered wiring layer and is different from the first through hole, or a structure in which films including electrically-conductive materials are formed on inner walls of the first through hole and the second through hole.

13 . The solid-state imaging device according to claim 11 , wherein the via has a structure in which an electrically-conductive material is embedded in one through hole provided to contact the predetermined wiring line in the third multi-layered wiring layer and expose the predetermined wiring line in the first multi-layered wiring layer, or one through h

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Hashiguchi Hideto
• Shohji Reijiroh
• Horikoshi Hiroshi
• Mitsuhashi Ikue
• Iijima Tadashi
• Kameshima Takatoshi
• Ishida Minoru
• Haneda Masaki

Classifications

• H01L27/14645

  Electricity · mapped topic

• H01L27/14634

  Electricity · mapped topic

• H01L27/14612

  Electricity · mapped topic

• H01L27/14636 Primary

  Electricity · mapped topic

• H01L27/1464

  Electricity · mapped topic