Vertical non-volatile memory device with high aspect ratio

Patent metadata

Field	Value
Publication number	US-11031411-B2
Application number	US-201916505266-A
Country	US
Kind code	B2
Filing date	Jul 8, 2019
Priority date	Dec 19, 2016
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.

First claim

What is claimed is:

1. A non-volatile memory device comprising:
a substrate;
a lower insulating layer disposed on the substrate;
a multilayer structure of layers comprising gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, the multilayer structure having an opening extending vertically from the lower insulating layer, the opening including a first open portion and a second open portion,
wherein the first open portion extends through at least one of the layers of the multilayer structure from the lower insulating layer, and the second open portion is located on the first open portion and extends vertically upwardly from the first open portion in the multilayer structure, and the opening has a first width at the first open portion and a second width at the second open portion, the second width being less than the first width;
a gate dielectric extending along an inner surface and a lower surface defining a side and a bottom of the opening, respectively, wherein the gate dielectric is located on the lower insulating layer; and
a channel structure disposed on the gate dielectric within the opening as extending along the inner surface and the lower surface defining the side and the bottom of the opening, the channel structure extending through the lower insulating layer and the gate dielectric and electrically connected to the substrate,
wherein a lower surface of the gate dielectric contacts an upper surface of the lower insulating layer in the bottom of the opening.

2. The non-volatile memory device of claim 1 , wherein a side surface of the gate dielectric contacts a side surface of the channel structure in the first open portion.

3. The non-volatile memory device of claim 1 , wherein a distance between inner surfaces of the gate dielectric in the first open portion is greater than a distance between the inner surfaces of the gate dielectric layer in the second open portion.

4. The non-volatile memory device of claim 1 , wherein the channel structure includes a first channel layer on the gate dielectric layer and a second channel layer electrically connected to the substrate on the first channel layer.

5. The non-volatile memory device of claim 4 , wherein the second channel layer includes a contact portion that extends through the first channel layer.

6. The non-volatile memory device of claim 1 , wherein a distance between inner surfaces of the channel structure in the first open portion is greater than a distance between the inner surfaces of the channel structure in the second open portion.

7. The non-volatile memory device of claim 1 , wherein the channel structure in the first open portion has a first region adjacent to the lower insulating layer, and a second region on the first region, and an inner surface of the first region is concave in a lateral direction.

8. The non-volatile memory device of claim 1 , wherein the first open portion has a first height, the second open portion has a second height, the first height with respect to the first width is less than or equal to 1, and the second height with respect to the second width is equal to or greater than 1.

9. The non-volatile memory device of claim 1 , further comprising a buried insulating layer disposed on the channel structure within the opening.

10. A non-volatile memory device comprising:
a substrate;
a lower insulating layer disposed on the substrate;
a multilayer structure of layers comprising gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, the multilayer structure having an opening extending vertically from the lower insulating layer, the opening including a first open portion and a second open portion,
wherein the first open portion extends through at least one of the layers of the multilayer structure from the lower insulating layer, and the second open portion is located on the first open portion and extends vertically upwardly from the first open portion in the multilayer structure, and the opening has a first width at the first open portion and a second width at the second open portion, the second width being less than the first width;
a gate dielectric extending along an inner surface and a lower surface defining a side and a bottom of the opening, respectively; and
a channel structure disposed on the gate dielectric within the opening as extending along the inner surface and the lower surface defining the side and the bottom of the opening, the channel structure extending through the lower insulating layer and electrically connected to the substrate,
wherein the channel structure includes a first channel layer on the gate dielectric and a second channel layer electrically connected to the substrate on the first channel layer,
wherein a distance from a bottom surface of the gate dielectric to an upper surface of the substrate is smaller than a distance between an upper surface of the second channel layer and an upper surface of the lower insulating layer in the first open portion, and
wherein a lower surface of the gate dielectric contacts an upper surface of the lower insulating layer in the bottom of the opening.

11. The non-volatile memory device of claim 10 , wherein a thickness of the first channel layer and the second channel layer on the lower insulating layer is larger than a thickness of the lower insulating layer on the substrate.

12. The non-volatile memory device of claim 10 , wherein a side surface of the gate dielectric contacts a side surface of the second channel structure layer in the first open portion.

13. The non-volatile memory device of claim 10 , further comprising a buried insulating layer disposed on the channel structure within the opening, wherein the buried insulating layer has a void therein, the void being located within the first open portion or the second open portion of the opening.

14. A non-volatile memory device comprising:
a substrate;
a lower insulating layer disposed on the substrate;
a multi-layered structure on the lower insulating layer, the multi-layered structure including a first structure and a second structure, wherein the multi-layered structure has an opening extending therein, the opening includes a first open portion extending through the first structure, and a second open portion extending through the second structure, the opening has a first width at the first open portion and a second width at the second open portion, the second width is less than the first width;
a gate dielectric layer extending along an inner surface and a lower surface defining a side and a bottom of the opening, respectively; and
a channel structure disposed on the gate dielectric layer and on the inner surface and the lower surface defining the side and the bottom of the opening, and the channel structure extending through the lower insulating layer and electrically connected to the substrate,
wherein the lower insulating layer and the gate dielectric layer contact a side surface of the channel structure.

15. The non-volatile memory device of claim 14 , wherein the channel structure includes a first channel layer on the gate dielectric layer extending along the inner surface defining the side of the opening, and a second channel layer on the first channel layer,
the second channel layer electrically connected to the substrate.

16. The non-volatile memory device of claim 15 , wherein the second channel layer extends through the lower insulating layer and into the substrate.

17. The non-volatile memory device of claim 14 , wherein the first open portion has a f

Assignees

• Samsung Electronics Co Ltd

Inventors

• Son Young-Hwan
• Jang Jae-Hoon
• Han Jee-Hoon

Classifications

• H10D30/798

  being provided in or under the channel regions · CPC title

• H10D62/213

  Channel regions of field-effect devices · CPC title

• H01L27/11524

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic