Contact interlayer dielectric replacement with improved SAC cap retention

Patent metadata

Field	Value
Publication number	US-11024536-B2
Application number	US-201916387687-A
Country	US
Kind code	B2
Filing date	Apr 18, 2019
Priority date	Apr 18, 2019
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

Embodiments of the present invention are directed to reducing the effective capacitance between active devices at the contact level. In a non-limiting embodiment of the invention, an interlayer dielectric is replaced with a low-k material without damaging a self-aligned contact (SAC) cap. A gate can be formed over a channel region of a fin. The gate can include a gate spacer and a SAC cap. Source and drain regions can be formed adjacent to the channel region. A contact is formed on the SAC cap and on surfaces of the source and drain regions. A first dielectric layer can be recessed to expose a sidewall of the contact and a sidewall of the gate spacer. A second dielectric layer can be formed on the recessed surface of the first dielectric layer. The second dielectric layer can include a dielectric material having a dielectric constant less than the first dielectric layer.

First claim

What is claimed is:

1. A method for forming a semiconductor device, the method comprising:
forming a gate over a channel region of a fin, the gate comprising a gate spacer and a gate hard mask;
forming a source adjacent to a first end of the channel region and a drain adjacent to a second end of the channel region;
forming a contact on the gate hard mask, the contact comprising a first portion on a surface of the source and a second portion on a surface of the drain;
forming a first dielectric layer on a sidewall of the gate spacer, the first dielectric layer comprising a first dielectric material having a first dielectric constant;
forming an oxide hard mask on a surface of the gate hard mask;
planarizing the contact to a surface of the oxide hard mask such that an overburden remains over the gate hard mask;
recessing the first dielectric layer to expose a sidewall of the contact and a sidewall of the gate spacer; and
forming a second dielectric layer on a recessed surface of the first dielectric layer, the second dielectric layer comprising a second dielectric material having a second dielectric constant less than the first dielectric constant.

2. The method of claim 1 , wherein the contact prevents erosion of the gate hard mask when recessing the first dielectric layer.

3. The method of claim 1 , wherein the contact comprises cobalt or tungsten and the gate hard mask comprises silicon nitride.

4. The method of claim 1 , wherein the first dielectric material comprises silicon oxide and the first dielectric constant is greater than or equal to 3.

5. The method of claim 4 , wherein the second dielectric material comprises a low-k dielectric material and the second dielectric constant is less than 3.

6. The method of claim 2 , wherein recessing the first dielectric layer damages a top portion of the contact.

7. The method of claim 1 further comprising selectively depositing a selective cap on a surface of the contact.

8. The method of claim 1 further comprising depositing a liner over a surface of the contact and on the recessed surface of the first dielectric layer.

9. A method for forming a semiconductor device, the method comprising:
forming a gate over a channel region of a fin;
forming a self-aligned contact (SAC) cap over the gate;
forming a contact on the SAC cap;
forming a first dielectric layer on a sidewall of the gate, the first dielectric layer comprising a first dielectric material having a first dielectric constant;
recessing the first dielectric layer to expose a sidewall of the contact; and
forming a second dielectric layer on a recessed surface of the first dielectric layer, the second dielectric layer comprising a second dielectric material having a second dielectric constant less than the first dielectric constant.

10. The method of claim 9 , wherein the first dielectric material comprises silicon oxide and the first dielectric constant is about 3 .

11. The method of claim 10 , wherein the second dielectric material comprises a low-k dielectric material and the second dielectric constant is less than 3.

12. The method of claim 9 further comprising planarizing the contact such that an overburden remains over the SAC cap.

13. The method of claim 9 further comprising selectively depositing a selective cap on a surface of the contact.

14. The method of claim 9 further comprising depositing a liner over a surface of the SAC cap, a surface of the contact, and on the recessed surface of the first dielectric layer.

Assignees

• IBM

Inventors

• Carr Adra
• Kamineni Vimal
• Xie Ruilong
• Greene Andrew
• Cave Nigel
• Basker Veeraraghavan

Classifications

• H10W20/093

  by modifying materials of the dielectric parts · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/46

  comprising air gaps · CPC title