Self-aligned low dielectric constant gate cap and a method of forming the same

Patent metadata

Field	Value
Publication number	US-2018090375-A1
Application number	US-201715837236-A
Country	US
Kind code	A1
Filing date	Dec 11, 2017
Priority date	Dec 15, 2015
Publication date	Mar 29, 2018
Grant date	—

Abstract

According to an embodiment of the present invention, self-aligned gate cap, comprises a gate located on a substrate; a gate cap surrounding a side of the gate; a contact region self-aligned to the gate; and a low dielectric constant oxide having a dielectric constant of less than 3.9 located on top of the gate. According to an embodiment of the present invention, a method of forming a self-aligned contact comprises removing at least a portion of an interlayer dielectric layer to expose a top surface of a gate cap located on a substrate; recessing the gate cap to form a recessed area; depositing a low dielectric constant oxide having a dielectric constant of less than 3.9 in the recessed area; and polishing a surface of the low dielectric constant oxide to expose a contact area.

First claim

What is claimed is:

1 . A method of forming a self-aligned contact, comprising:
forming a gate on a substrate; forming a conductive contact on the substrate and adjacent to the gate; after forming the conductive contact, removing at least a portion of an interlayer dielectric layer to expose a top surface of a gate cap located on the substrate and on a top surface of the gate; partially recessing the gate cap to form a recessed area such that the top surface of the gate is not exposed, the recessed gate cap comprising a thickness of 1 to 20 nanometers on the top surface of the gate; depositing a low dielectric constant oxide having a dielectric constant of 2.8 to 3.5 on a surface of the partially recessed gate cap in the recessed area; and polishing a surface of the low dielectric constant oxide to expose a surface of the conductive contact; wherein removing at least a portion of an interlayer dielectric layer comprises dry etching the interlayer dielectric layer; wherein the low dielectric constant oxide comprises a porous silicon dioxide or a doped silicon dioxide.

Assignees

• IBM

Inventors

• Pranatharthiharan Balasubramanian
• Ok Injo
• Surisetty Charan V V S

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/665

  Porous materials · CPC title

• H10W20/071

  of dielectric parts thereof · CPC title

• H10W20/063 Primary

  by forming conductive members before forming protective insulating material · CPC title