Method and structure for forming MOSFET with reduced parasitic capacitance

Patent metadata

Field	Value
Publication number	US-9985107-B2
Application number	US-201615196591-A
Country	US
Kind code	B2
Filing date	Jun 29, 2016
Priority date	Jun 29, 2016
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

A method (and structure) of fabricating an MOSFET (metal-oxide-semiconductor field-effect transistor), includes, on a gate structure coated with a high-k sidewall spacer film, etching off the high-k sidewall spacer film from a top surface of the gate structure and from a portion of vertical walls of the gate structure. The etched-off high-k sidewall spacer film on the vertical walls is replaced with an ultra low-k material.

First claim

What is claimed is:

1. A finFET (fin Field Effect Transistor) comprising:
a gate structure comprising a gate contact covering a high impedance film layer;
a fin channel directly under said gate structure such that a movement of carriers is controlled by a voltage in said gate contact;
a source epitaxial region covered by a source contact metal layer, adjacent to a first side of said gate structure; and
a drain epitaxial region covered by a drain contact metal layer, adjacent to a second side of said gate structure and opposing said first side,
wherein said gate structure further comprises a gate sidewall spacer layer, comprising an upper portion and a lower portion, to isolate said gate from said source contact metal layer and said drain contact metal layer,
wherein said lower portion of said gate sidewall spacer layer comprises a material having a high-k value and said upper portion of said gate sidewall spacer layer comprises a material having an ultra low-k material and a first side surface of the ultra low-k material directly contacts a side surface of a metal layer comprising said gate contact and a second side surface of the ultra low-k material directly contacts one of a side surface of the source contact metal layer or a side surface of the drain contact metal layer along an entirety of a vertical dimension of the side surface of the source contact metal layer or the drain contact metal layer, and
wherein a thickness of the upper portion is approximately the same as a thickness of the lower portion; and
wherein a height of said lower portion of said gate sidewall spacer layer is lower than a height of said source epitaxial region and a height of said drain epitaxial region such that said gate sidewall spacer layer further comprises a middle portion comprising an air spacer between said gate structure and said source epitaxial region and between said gate structure and said drain epitaxial region, and
wherein said air spacer results from having a width of said lower portion being predetermined to provide a high-aspect ratio opening that traps an air gap when said upper portion is formed, the air spacer thereby being below a top surface of said source epitaxial region and below a top surface of said drain epitaxial region.

2. The finFET of claim 1 , wherein said lower portion comprises a high-k sidewall spacer layer comprising a SiBCN (Silicon-Boron-Carbon-Nitride) thin film.

3. The finFET of claim 1 , wherein said ultra low-k material comprises at least one of:
SiCOH, a thin film comprising silicon Si, carbon C, oxygen O, and hydrogen H;
an organosilica glass (OSG);
a porous xerogel; and
a mesoporous silica film (MCM).

4. A MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) comprising:
a gate structure comprising a gate contact covering a high impedance film layer;
a channel directly under said gate structure such that a movement of carriers is controlled by a voltage in said gate contact;
a source epitaxial region covered by a source contact metal layer, adjacent to a first side of said gate structure; and
a drain epitaxial region covered by a drain contact metal layer, adjacent to a second side of said gate structure and opposing said first side,
wherein said gate structure further comprises a gate sidewall spacer layer to isolate said gate from said source contact metal layer and from said drain contact metal layer,
wherein said gate sidewall spacer layer comprises an upper portion and a lower portion between said gate structure and said drain contact metal layer and between said gate structure and said source contact metal layer,
wherein the upper portion comprises a material having an ultra low-k material, and a first side surface of the ultra low-k material directly contacts a first side surface of a metal comprising said gate contact and a second side surface of the ultra low-k material directly contacts a side surface of one of the source contact metal layer and the drain contact metal layer along an entirety of a vertical dimension of the side surface of the source contact metal layer or the drain contact metal layer, and wherein a thickness of the upper portion is approximately the same as a thickness of the lower portion; and
wherein said gate sidewall spacer layer comprises a portion between said gate structure and said source epitaxial region and between said gate structure and said drain epitaxial region with a material having a high-k value
wherein said gate sidewall spacer layer further comprises a middle portion comprising an air spacer between said gate structure and said source epitaxial region and between said gate structure and said drain epitaxial region,
wherein said air spacer results from having a width of said lower portion being predetermined to provide a high-aspect ratio opening that traps an air gap when said upper portion is formed, the air spacer thereby being below a top surface of said source epitaxial region and below a top surface of said drain epitaxial region.

5. The MOSFET of claim 4 , wherein said lower portion comprises a high-k sidewall spacer film comprising a SiBCN (Silicon-Boron-Carbon-Nitride) thin film.

6. The MOSFET of claim 4 , wherein said ultra low-k material comprises at least one of:
SiCOH, a thin film comprising silicon Si, carbon C, oxygen O, and hydrogen H;
an organosilica glass (OSG);
a porous xerogel; and
a mesoporous silica film (MCM).

Assignees

• IBM

Inventors

• Cheng Kangguo
• Xu Peng
• Zhang Chen

Classifications

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H01L29/66689

  Electricity · mapped topic

• H01L29/51 Primary

  Electricity · mapped topic

• H01L23/5329

  Electricity · mapped topic