Semiconductor pattern detecting apparatus

Patent metadata

Field	Value
Publication number	US-11017525-B2
Application number	US-201916541380-A
Country	US
Kind code	B2
Filing date	Aug 15, 2019
Priority date	Dec 6, 2018
Publication date	May 25, 2021
Grant date	May 25, 2021

Abstract

A semiconductor pattern detecting apparatus is provided. The semiconductor pattern detecting apparatus includes a stage configured to position a wafer formed with a semiconductor pattern, the stage extending in a first direction and a second direction perpendicular to the first direction, an electron emitter configured to irradiate first electrons on the semiconductor pattern, an electrode configured to generate an electric field to induce an electric potential on a surface of the semiconductor pattern, a detector configured to detect second electrons emitted from the semiconductor pattern, an imager configured to obtain a plurality of first images by using the second electrons detected by the detector, and at least one controller configured to apply a first voltage and a second voltage different from the first voltage to the electrode alternately and repeatedly and to generate a second image by combining the plurality of first images, wherein the imager is so configured that each of the plurality of first images are obtained when the first voltage is applied to the electrode.

First claim

What is claimed is:

1. A semiconductor pattern detecting apparatus, comprising:
a stage configured to position a wafer formed with a semiconductor pattern, the stage extending in a first direction and a second direction perpendicular to the first direction;
an electron emitter configured to irradiate first electrons on the semiconductor pattern;
an electrode configured to generate an electric field to induce an electric potential on a surface of the semiconductor pattern;
a detector configured to detect second electrons emitted from the semiconductor pattern;
an imager configured to obtain a plurality of first images by using the second electrons detected by the detector; and
at least one controller configured to apply a first voltage and a second voltage different from the first voltage to the electrode alternately and repeatedly and to generate a second image by combining the plurality of first images,
wherein the imager is so configured that each of the plurality of first images is obtained when the first voltage is applied to the electrode.

2. The semiconductor pattern detecting apparatus of claim 1 , wherein the second electrons are secondary electrons.

3. The semiconductor pattern detecting apparatus of claim 1 , wherein the electrode is disposed between the stage and the electron emitter.

4. The semiconductor pattern detecting apparatus of claim 1 , wherein time lengths of repeatedly applying the second voltage to the electrode are the same as each other.

5. The semiconductor pattern detecting apparatus of claim 4 , wherein each of the first images has a plane shape extending in parallel with an upper surface of the stage.

6. The semiconductor pattern detecting apparatus of claim 4 , wherein each of the first images has a line shape extending in the second direction.

7. The semiconductor pattern detecting apparatus of claim 6 , wherein the second image is formed by combining the plurality of first images sequentially formed in the first direction.

8. The semiconductor pattern detecting apparatus of claim 4 , wherein each of the first images has a dot shape.

9. The semiconductor pattern detecting apparatus of claim 8 , wherein the second image is formed by combining the plurality of first images formed sequentially in the first direction and the second direction.

10. The semiconductor pattern detecting apparatus of claim 1 , wherein the second voltage is higher than the first voltage.

11. The semiconductor pattern detecting apparatus of claim 1 , wherein the second voltage is lower than the first voltage.

12. A semiconductor pattern detecting apparatus, comprising:
a stage configured to position a wafer formed with a semiconductor pattern, the stage extending in a first direction and a second direction perpendicular to the first direction;
an electron emitter configured to emit electrons on the semiconductor pattern;
an electrode configured to generate an electric field to induce an electric potential on a surface of the semiconductor pattern;
a detector configured to detect secondary electrons generated from the semiconductor pattern;
an imager configured to obtain a plurality of first images formed in a third direction perpendicular to an upper surface of the stage by using the secondary electrons detected by the detector; and
at least one controller configured to apply a first voltage and a second voltage different from the first voltage to the electrode alternately and repeatedly and to generate a second image by combining the plurality of first images,
wherein the imager is so configured that the plurality of first images are obtained when the first voltage is applied to the electrode, and
wherein the at least one controller is so configured that time lengths of repeatedly applying the second voltage to the electrode sequentially decrease while the plurality of first images are obtained.

13. The semiconductor pattern detecting apparatus of claim 12 , wherein each of the first images has a plane shape.

14. The semiconductor pattern detecting apparatus of claim 13 , wherein the second image is formed by combining the plurality of first images sequentially formed in the first direction.

15. The semiconductor pattern detecting apparatus of claim 12 , wherein each of the first images has a line shape.

16. The semiconductor pattern detecting apparatus of claim 15 , wherein the second image is formed by combining the plurality of first images formed sequentially in the first direction and the second direction.

17. A semiconductor pattern detecting apparatus, comprising:
a stage configured to receive a substrate formed with a semiconductor pattern comprising a first pattern and a second pattern containing different materials from each other;
an electron emitter configured to emit electrons on the semiconductor pattern;
an electrode configured to generate an electric field to induce an electric potential on a surface of the semiconductor pattern;
a detector configured to measure a first capacitance of a first region comprising the first pattern and to measure a second capacitance of a second region comprising the second pattern;
an imager configured to obtain a plurality of first images by using the first capacitance and the second capacitance; and
at least one controller configured to apply a first voltage and a second voltage different from the first voltage to the electrode alternately and repeatedly and to generate a second image by combining the plurality of first images,
wherein the imager is so configured that the plurality of first images are obtained when the first voltage is applied to the electrode.

18. The semiconductor pattern detecting apparatus of claim 17 , wherein the electrode is disposed between the stage and the electron emitter.

19. The semiconductor pattern detecting apparatus of claim 17 , wherein time lengths of repeatedly applying the second voltage to the electrode are the same as each other.

20. The semiconductor pattern detecting apparatus of claim 17 , wherein time lengths of repeatedly applying the second voltage sequentially decrease while obtaining the plurality of first images.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ahn Jae Hyung
• Kim Souk
• Song Joon Seo
• Sohn Young Hoon
• Yang Yu Sin

Classifications

• G06V10/10

  Image acquisition (document image scanning and transmission H04N1/00; control of digital cameras H04N23/60) · CPC title

• G06F18/28

  Determining representative reference patterns, e.g. by averaging or distorting; Generating dictionaries · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• G06T7/001 Primary

  using an image reference approach · CPC title