Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-11011652-B2
Application number	US-202016847912-A
Country	US
Kind code	B2
Filing date	Apr 14, 2020
Priority date	Jul 8, 2011
Publication date	May 18, 2021
Grant date	May 18, 2021

Abstract

Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a gate electrode;
a gate insulating film over the gate electrode;
a first oxide semiconductor layer over and in direct contact with the gate insulating film;
a second oxide semiconductor layer over and in direct contact with the first oxide semiconductor layer;
a source electrode over and in direct contact with the second oxide semiconductor layer;
a drain electrode over and in direct contact with the second oxide semiconductor layer; and
an oxide insulating layer over the source electrode and the drain electrode,
wherein the oxide insulating layer is in direct contact with the second oxide semiconductor layer between the source electrode and the drain electrode,
wherein the first oxide semiconductor layer comprises indium, tin, and zinc,
wherein the second oxide semiconductor layer comprises indium, gallium, and zinc,
wherein an energy gap of the first oxide semiconductor layer is smaller than an energy gap of the second oxide semiconductor layer, and
wherein a c-axis of a crystal in the second oxide semiconductor layer is perpendicular to an upper surface of the second oxide semiconductor layer.

2. The semiconductor device according to claim 1 , wherein the second oxide semiconductor layer is in direct contact with a side surface of the first oxide semiconductor layer.

3. The semiconductor device according to claim 1 , wherein the oxide insulating layer comprises aluminum and oxygen.

4. The semiconductor device according to claim 1 , wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises an oxygen excess region.

5. The semiconductor device according to claim 1 , wherein the side surface of the first oxide semiconductor layer is along a channel width direction.

6. The semiconductor device according to claim 1 , further comprising:
a first transistor comprising silicon in a channel formation region; and
a first insulating layer over the first transistor and under the first oxide semiconductor layer.

7. A semiconductor device comprising:
a gate electrode;
a gate insulating film over the gate electrode;
a first oxide semiconductor layer over and in direct contact with the gate insulating film;
a second oxide semiconductor layer over and in direct contact with the first oxide semiconductor layer;
a source electrode over and in direct contact with the second oxide semiconductor layer;
a drain electrode over and in direct contact with the second oxide semiconductor layer; and
an oxide insulating layer over the source electrode and the drain electrode,
wherein the oxide insulating layer is in direct contact with the second oxide semiconductor layer between the source electrode and the drain electrode,
wherein the first oxide semiconductor layer comprises indium, tin, and zinc,
wherein the second oxide semiconductor layer comprises indium, gallium, and zinc, and
wherein an energy gap of the first oxide semiconductor layer is smaller than an energy gap of the second oxide semiconductor layer.

8. The semiconductor device according to claim 7 , wherein the second oxide semiconductor layer is in direct contact with a side surface of the first oxide semiconductor layer.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Shinohara Satoshi

Classifications

• H10B41/70

  the floating gate being an electrode shared by two or more components · CPC title

• H10D86/425

  having different crystal properties in different TFTs or within an individual TFT · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/431

  having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title