Semiconductor device with insulating layers forming a bonding plane between first and second circuit components, method of manufacturing the same, and electronic device

Patent metadata

Field	Value
Publication number	US-10998370-B2
Application number	US-201916558863-A
Country	US
Kind code	B2
Filing date	Sep 3, 2019
Priority date	Sep 13, 2018
Publication date	May 4, 2021
Grant date	May 4, 2021

Abstract

A semiconductor device comprising a first circuit component and a second circuit component, the first circuit component having a first wiring structure formed by stacking one or more wiring layers and one or more insulating layers on a first semiconductor substrate, the second circuit component having a second wiring structure formed by stacking one or more wiring layers and one or more insulating layers on a second semiconductor substrate, the first and second wiring structures being bonded to each other, their bonding planes being composed of oxygen atoms and carbon atoms and/or nitrogen atoms bonded to silicon atoms, and, numbers of their atoms satisfying a predetermined equation.

First claim

What is claimed is:

1. A semiconductor device comprising a first circuit component and a second circuit component,
wherein the first circuit component has a first semiconductor substrate and a first wiring structure formed by stacking one or more wiring layers and one or more insulating layers on the first semiconductor substrate,
wherein the second circuit component has a second semiconductor substrate and a second wiring structure formed by stacking one or more wiring layers and one or more insulating layers on the second semiconductor substrate,
wherein the first wiring structure and the second wiring structure of the first circuit component and the second circuit component are bonded to each other, and
wherein the insulating layers of the first wiring structure and the second wiring structure forming a bonding plane between the first circuit component and the second circuit component are both composed of silicon atoms, oxygen atoms, and at least one selected from the group consisting of carbon atoms and nitrogen atoms, and, letting numbers of oxygen atoms, carbon atoms, and nitrogen atoms in at least the insulating layers be N o , N c , and N N , respectively,
6×N O >3×N C +4×N N holds.

2. The semiconductor device according to claim 1 , wherein in at least one of the first wiring structure and the second wiring structure, the insulating layers further include hydrogen atoms.

3. The semiconductor device according to claim 1 , wherein in at least one of the first wiring structure and the second wiring structure, another insulating layer different from an uppermost insulating layer forming the bonding plane is formed of a material having a lower dielectric constant than that of the uppermost insulating layer.

4. The semiconductor device according to claim 3 , wherein at least a portion of the another insulating layer is made of a material having a dielectric constant of 4.5 or less.

5. The semiconductor device according to claim 1 , wherein in at least one of the first wiring structure and the second wiring structure, an uppermost wiring layer forming the bonding plane in a plurality of wiring layers is covered with a barrier metal, and a lower surface of an uppermost insulating layer forming the bonding plane in a plurality of insulating layers is positioned higher than a lower surface of the uppermost wiring layer.

6. The semiconductor device according to claim 1 , wherein in at least one of the first wiring structure and the second wiring structure, an uppermost wiring layer forming the bonding plane in a plurality of wiring layers is covered with a barrier metal, and a lower surface of an uppermost insulating layer forming the bonding plane in a plurality of insulating layers is positioned lower than a lower surface of the uppermost wiring layer.

7. The semiconductor device according to claim 1 , wherein in at least one of the first wiring structure and the second wiring structure, another insulating layer different from an uppermost insulating layer forming the bonding plane is configured by a composition similar to the uppermost insulating layer.

8. The semiconductor device according to claim 1 , wherein the insulating layers forming the bonding plane include silicon oxide (SiO 2 ), silicon carbide (SiC), and silicon nitride (Si 3 N 4 ).

9. The semiconductor device according to claim 1 , wherein N c >0 and N N >0 is satisfied.

10. The semiconductor device according to claim 9 , wherein the insulating layers forming the bonding plane are configured such that a concentration of both carbon atoms and nitrogen atoms is 6.5×10 20 [atoms/cm 3 ] or more.

11. The semiconductor device according to claim 1 , wherein the semiconductor device is a solid-state imaging device including a plurality of pixels, and
wherein each of the plurality of pixels includes:
a photoelectric conversion element;
a floating diffusion;
a first transistor configured to transfer a charge of the photoelectric conversion element to the floating diffusion; and
a second transistor configured to output a signal corresponding to a voltage of the floating diffusion,
wherein the photoelectric conversion element, the floating diffusion, and the first transistor are provided on the first semiconductor substrate, and
wherein the second transistor is provided on the second semiconductor substrate.

12. An electronic device, comprising:
the semiconductor device according to claim 1 ; and
a processor configured to process a signal from the semiconductor device.

13. A method for manufacturing a semiconductor device, the method comprising:
preparing a first circuit component having a first semiconductor substrate and a first wiring structure formed by stacking one or more wiring layers and one or more insulating layers on the first semiconductor substrate;
preparing a second circuit component having a second semiconductor substrate and a second wiring structure formed by stacking one or more wiring layers and one or more insulating layers on the second semiconductor substrate; and
bringing the first wiring structure and the second wiring structure into contact with each other to cause the first circuit component and the second circuit component to bond,
wherein in each of the preparing of the first circuit component and the preparing of the second circuit component, when the insulating layers of the first wiring structure and the second wiring structure forming a bonding plane between the first circuit component and the second circuit component are both composed of silicon atoms, oxygen atoms, and at least one selected form the group consisting of carbon atoms and nitrogen atoms, and, letting numbers of oxygen atoms, carbon atoms, and nitrogen atoms in at least the bonding plane be N o , N c , and N N , respectively,
6×N O >3×N C +4×N N holds.

14. The method according to claim 13 , wherein in each of the preparing of the first circuit component and the preparing of the second circuit component, the insulating layer forming the bonding plane is formed by plasma CVD using trimethoxysilane and nitrous oxide.

Assignees

• Canon Kk

Inventors

• Ikakura Hiroshi
• Ogino Takumi

Classifications

• H10P14/32

  characterised by intermediate layers between substrates and deposited layers · CPC title

• H10P14/29

  characterised by the substrates · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title