Semiconductor device and solid-state imaging device

Patent metadata

Field	Value
Publication number	US-2016233264-A1
Application number	US-201415023783-A
Country	US
Kind code	A1
Filing date	Sep 19, 2014
Priority date	Oct 4, 2013
Publication date	Aug 11, 2016
Grant date	—

Abstract

The present technology relates to a semiconductor device and a solid-state imaging device of which crack resistance can be improved in a simpler way. The semiconductor device has an upper substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and a second substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and is joined to the upper substrate. In addition, a pad for wire bonding or probing is formed in the upper substrate, and pads for protecting corner or side parts of the pad for wire bonding or probing are radially laminated and provided in each of the wiring layers between the pad and the Si substrate of the lower substrate. The present technology can be applied to a solid-state imaging device.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a first substrate which has a plurality of wiring layers; and a second substrate which has a plurality of wiring layers and is bonded to the first substrate, wherein metal wiring which is formed of a metal in each wiring layer is provided between a pad that is provided in one substrate of the first substrate and the second substrate and a wiring layer on the other substrate side that is closest to the other substrate, and in a wiring layer on the other substrate side adjacent to the pad or the metal wiring, other metal wiring is disposed in at least a corner part of the pad or the metal wiring in an upper layer.

2 . The semiconductor device according to claim 1 , wherein the pad is a pad for wire bonding or probing.

3 . The semiconductor device according to claim 1 , wherein the pad is provided in a substrate of the first substrate and the second substrate on a side on which wire bonding or probing is performed.

4 . The semiconductor device according to claim 1 , wherein the first substrate and the second substrate are bonded together by bonding Cu wiring provided on a surface of the first substrate and Cu wiring provided on a surface of the second substrate.

5 . The semiconductor device according to claim 1 , wherein a region that does not contain a member that forms the metal wiring is provided at a center portion of a bonding-surface-side surface of the metal wiring on a bonding surface of the first substrate and the second substrate.

6 . The semiconductor device according to claim 1 , wherein the other metal wiring is disposed at least in the vicinity of the pad or the metal wiring.

7 . The semiconductor device according to claim 1 , wherein an insulating film is provided between a substrate which constitutes the other substrate and on which a plurality of wiring layers are laminated and the metal wiring.

8 . The semiconductor device according to claim 1 , wherein a region of a portion which comes into contact with the metal wiring of a substrate, which constitutes the other substrate and on which a plurality of wiring layers are laminated, is electrically separated from another region of the substrate by an insulator that is embedded in the substrate.

9 . The semiconductor device according to claim 1 , wherein, in a wiring layer in which contacts that connect a substrate, which constitutes the one substrate and on which a plurality of wiring layers are laminated, to wiring provided in a wiring layer of the one substrate are formed, the pad is formed of the same metal as the contacts.

10 . The semiconductor device according to claim 1 , wherein, after bonding of the first substrate and the second substrate, the pad is formed in a portion of a stopper layer provided in a wiring layer inside the one substrate removed by forming an opening.

11 . The semiconductor device according to claim 1 , further comprising:
a via which is provided in a substrate, which constitutes the one substrate and on which a plurality of wiring layers are laminated, penetrates the substrate, and is connected to the metal wiring, wherein the pad is provided above the via of a surface of the one substrate.

12 . The semiconductor device according to claim 1 , wherein the pad is provided in a portion of an opening of the one substrate, and formed using a metal mask having a narrower opening than the opening.

13 . The semiconductor device according to claim 12 , wherein an insulating film is formed on a side surface of the opening of the one substrate.

14 . The semiconductor device according to claim 1 , wherein wiring that is formed of a different metal from the pad is embedded in the pad, and the metal wiring is provided in a wiring layer on the other substrate side of the wiring.

15 . The semiconductor device according to claim 14 , wherein the wiring is provided as the metal wiring in at least a corner part of the pad in a wiring layer on the other substrate side adjacent to the pad.

16 . The semiconductor device according to claim 15 , wherein a region that does not contain the member that forms the wiring is provided in a center portion of a surface of the wiring.

17 . A semiconductor device comprising:
a first substrate which has a plurality of wiring layers; and a second substrate which has a plurality of wiring layers and is bonded to the first substrate, wherein a Cu pad for bonding provided on a bonding surface to the second substrate and Cu vias which penetrate a plurality of wiring layers and connect the Cu pad for bonding and C wiring are provided in the first substrate, and wherein another Cu pad for bonding which is provided on a bonding surface to the first substrate and bonded to the Cu pad for bonding is provided in the second substrate.

18 . A solid-state imaging device comprising:
a first substrate which has a plurality of wiring layers; and a second substrate which has a plurality of wiring layers and is bonded to the first substrate, wherein metal wiring which is formed of a metal in each of wiring layers is provided between a pad that is provided in one substrate of the first substrate and the second substrate and a wiring layer on the other substrate side that is closest to the other substrate, and in a wiring layer on the other substrate side adjacent to the pad or the metal wiring, other metal wiring is disposed in at least a corner part of the pad or the metal wiring in an upper layer.

Assignees

• Sony Corp

Inventors

• Kagawa Yoshihisa
• Fujii Nobutoshi
• Fukasawa Masanaga
• Kaneguchi Tokihisa
• Hagimoto Yoshiya
• Aoyagi Kenichi
• Mitsuhashi Ikue

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/792

  between multiple chips · CPC title