Semiconductor device and method for production of semiconductor device

Patent metadata

Field	Value
Publication number	US-9679937-B2
Application number	US-201614992865-A
Country	US
Kind code	B2
Filing date	Jan 11, 2016
Priority date	Aug 24, 2009
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first semiconductor substrate including:
a first interlayer dielectric film,
a first wiring layer,
an imaging device,
a first pad formed at least partially within the first interlayer dielectric film, and
a barrier layer formed between the first pad and the first interlayer dielectric film; and

a second semiconductor substrate including:
a second interlayer dielectric film,
a second wiring layer, and
a second pad formed at least partially within the second interlayer dielectric film such that a portion of the second semiconductor substrate is between a bottommost surface of the second pad and a surface of the second semiconductor substrate;
wherein,
the second semiconductor substrate further includes at least one of a logic device or a memory device,
one of the first pad or the second pad includes copper, and
the other of the first pad or the second pad includes at least one metallic material including Au, Ag, Al, Ta, Ti, W, Sn, Mo, Ni, In, Co, or an alloy of any of them.

2. The semiconductor device of claim 1 , wherein the barrier layer includes TiN or TaN.

3. The semiconductor device of claim 1 , wherein at least a portion of the barrier layer is in contact with at least a portion of the second pad.

4. The semiconductor device of claim 1 , wherein the first semiconductor substrate is bonded to the second semiconductor substrate.

5. The semiconductor device of claim 4 , wherein the first and second pads are in contact with one another.

6. The semiconductor device of claim 5 , wherein the second pad is formed from a metallic material that is less diffusible into the second interlayer dielectric film than the second wiring layer.

7. The semiconductor device of claim 1 , wherein the first pad has a surface exposed to and facing the second substrate, and wherein the second pad has a surface exposed to and facing the first substrate.

8. The semiconductor device of claim 7 , wherein the exposed surface of the second pad is larger than the exposed surface of the first pad.

9. The semiconductor device of claim 1 , wherein the second pad includes a base portion and a covering layer.

10. The semiconductor device of claim 1 , wherein the first pad is formed in a recess portion of the first interlayer dielectric film.

11. The semiconductor device of claim 10 , wherein the second pad is formed in a recess portion of the second interlayer dielectric film.

12. The semiconductor device of claim 11 , wherein the first pad has an exposed face that is flush with a boundary between the first interlayer dielectric film and the second interlayer dielectric film, wherein the second pad has an exposed face that is flush with the boundary between the first interlayer dielectric film and the second interlayer dielectric film, and wherein the exposed face of the second pad is larger than the exposed face of the first pad.

13. The semiconductor device of claim 1 , wherein the first pad includes copper.

14. The semiconductor device of claim 1 , wherein the barrier layer is effective to prevent metal of the first pad from diffusing into the first interlayer dielectric film.

15. The semiconductor device of claim 1 , wherein the second semiconductor substrate further includes a barrier layer formed between the second pad and the second interlayer dielectric film.

16. The semiconductor device of claim 1 , further comprising:
a diffusion preventing layer formed on the second interlayer dielectric film.

17. The semiconductor device of claim 16 , wherein the second pad is exposed through the diffusion preventing layer.

18. The semiconductor device of claim 17 , wherein the diffusion preventing layer is effective to prevent metal of the second pad from diffusing into the second interlayer dielectric film.

19. The semiconductor device of claim 1 , wherein a contacting region of the second pad is substantially equivalent in size to a contacting region of the first pad.

20. A semiconductor device comprising:
a first semiconductor substrate including an image device;
a first interlayer dielectric film and a first wiring layer provided at a first side of the first semiconductor substrate;
a first pad formed at least partially within the first interlayer dielectric film;
a barrier layer between the first pad and the first interlayer dielectric film;
a second semiconductor substrate including at least one of a logic device or a memory device;
a second interlayer dielectric film and a second wiring layer provided at a first side of the second semiconductor substrate;
a second pad formed at least partially within the second interlayer dielectric film such that a portion of the second semiconductor substrate is between a bottommost surface of the second pad and a surface of the second semiconductor substrate;
wherein,
one of the first pad or the second pad includes copper, and
the other of the first pad or the second pad includes at least one metallic material including Au, Ag, Al, Ta, Ti, W, Sn, Mo, Ni, In, Co, or an alloy of any of them.

21. A semiconductor device comprising:
a first semiconductor wafer including an imaging device, the first semiconductor wafer further including:
a first semiconductor substrate,
a first interlayer dielectric film and a first wiring layer provided at a first side of the first semiconductor substrate,
a first pad formed at least partially within the first interlayer dielectric film, and
a barrier layer between the first pad and the first interlayer dielectric film; and

a second semiconductor wafer including at least one of a logic device or a memory device, the second semiconductor wafer further including:
a second semiconductor substrate,
a second interlayer dielectric film and a second wiring layer provided at a first side of the second semiconductor substrate, and
a second pad formed at least partially within the second interlayer dielectric film such that a portion of the second semiconductor substrate is between a bottommost surface of the second pad and a surface of the second semiconductor substrate,

wherein,
one of the first pad or the second pad includes copper, and
the other of the first pad or the second pad includes at least one metallic material including Au, Ag, Al, Ta, Ti, W, Sn, Mo, Ni, In, Co, or an alloy of any of them.

Assignees

• Sony Corp

Inventors

• Okuyama Atsushi

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W90/00

  Package configurations · CPC title