Vertical field effect transistor replacement metal gate fabrication

Patent metadata

Field	Value
Publication number	US-10985073-B2
Application number	US-201916504849-A
Country	US
Kind code	B2
Filing date	Jul 8, 2019
Priority date	Jul 8, 2019
Publication date	Apr 20, 2021
Grant date	Apr 20, 2021

Abstract

A method for fabricating a semiconductor device includes forming a semiconductor structure including a substrate, a first vertical fin and a second vertical fin longitudinally spaced from the first vertical fin with each of the first and second vertical fin having a hardmask cap, and a bottom spacer layer on the substrate. The method further includes forming first and second bottom source/drains within the substrate respectively beneath the first and second vertical fins, forming first and second top source/drains respectively on the first and second vertical fins, forming a vertical oxide pillar between the first and second vertical fins, removing a portion of the oxide pillar to reduce a cross-sectional dimension to define a lower recessed region, and depositing a metal gate material about the first and second vertical fins wherein portions of the metal gate material are disposed within the recessed region of the oxide pillar.

First claim

The invention claimed is:

1. A method for fabricating a semiconductor device, comprising:
forming a semiconductor structure, including a substrate defining a longitudinal axis, a first vertical fin and a second vertical fin longitudinally spaced from the first vertical fin, each of the first and second vertical fins having a hardmask cap and a bottom spacer layer on the substrate;
forming a first bottom source/drain within the substrate beneath the first vertical fin and a second bottom source/drain within the substrate beneath the second vertical fin;
forming a first top source/drain on the first vertical fin and a second top source/drain on the second vertical fin;
forming a vertical oxide pillar between the first and second vertical fins;
removing a portion of the oxide pillar to reduce a cross-sectional dimension of a lower end of the oxide pillar to define a recessed region of the oxide pillar;
depositing at least one metal gate material about the first and second vertical fins to form first and second metal gate structures about respective first and second vertical fins, wherein portions of the at least one metal gate material are disposed within the recessed region of the oxide pillar to form a first gate segment of the first metal gate structure and a second gate segment of the second metal gate structure;
removing a remaining portion of the oxide pillar to form a trench opening extending to the first and second metal gate segments; and
depositing a conductive contact material within the trench opening to form a gate contact, the gate contact coupled with both the first and second gate segments of the first and second metal gate structures.

2. The method of claim 1 , including, prior to depositing the gate material, depositing an oxide layer and a sacrificial liner onto the semiconductor structure including at least the first and second fins and the bottom spacer layer.

3. The method of claim 2 , including, prior to forming the oxide pillar, depositing a spacer between the first and second fins, wherein forming the oxide pillar includes depositing oxide fill material within the spacer.

4. The method of claim 3 , wherein removing a portion of the oxide pillar includes protecting the remaining portion of the oxide pillar with the spacer.

5. The method of claim 4 , wherein removing a portion of the oxide pillar includes utilizing a selective oxide etching process.

6. The method of claim 4 , including depositing a gate dielectric layer onto the semiconductor structure including on at least portions of the bottom spacer layer, at least portions of the first and second vertical fins and the recessed region of the oxide pillar.

7. The method of claim 6 , wherein the gate dielectric layer includes a conformal gate high-k liner.

8. The method of claim 6 , including removing the hardmask cap on each of the first and second vertical fins, and recessing the oxide layer and the sacrificial liner to a position below the first and second vertical fins.

9. The method of claim 8 , including depositing a capping material onto exposed portions of the sacrificial liner, and thereafter removing the oxide layer and the sacrificial liner prior to depositing the at least one metal gate material.

10. The method of claim 9 , wherein forming the semiconductor structure includes forming first and second pairs of the first and second vertical fins, the first vertical pins of the first pair being longitudinally adjacent to each other, the second vertical fins of the second pair being longitudinally adjacent to each other.

11. The method of claim 10 , wherein depositing a capping material includes disposing the capping material between the top source/drains of the first vertical fins of the first pair, the capping material being spaced from the bottom spacer layer wherein, upon removing the oxide layer and the sacrificial liner, a void is created extending continuously between the first vertical fins of the first pair below the capping material.

12. The method of claim 11 , wherein upon depositing the at least one metal gate material, the metal gate material extends across the void.

13. The method of claim 12 , including:
removing the capping material; and
opening and filling one or more additional trenches and/or via openings within the semiconductor structure with conductive material;
wherein the first fins of the first pair form a single fin device.

14. The method of claim 1 , wherein the first and second gate segments each define a L-shaped profile adjacent respective first and second vertical fins, the first and second gate segments defined by the recessed region of the oxide pillar.

15. A method for fabricating a semiconductor device, comprising:
forming a first vertical fin and a second vertical fin on a substrate of a semiconductor structure, the substrate defining a longitudinal axis, the first and second vertical pins being longitudinally spaced;
forming a first metal gate structure around the first vertical fin and a second metal gate structure around the second vertical fin, each of the metal gate structures having a gate segment defining a L-shaped profile configured to increase surface area for landing of a gate contact;
creating a trench at least partially through the semiconductor structure between the first and second vertical fins; and
depositing a conductive contact material within the trench to form a gate contact, the gate contact coupled with both of the gate segments of the first and second metal gate structures.

16. The method of claim 15 , wherein the first and second metal gate structures are each high-k metal gates.

17. The method of claim 15 , wherein the gate segment of the first metal gate structure is adjacent to the gate segment of the second metal gate structure.

18. The method of claim 15 , further comprising:
forming a vertical oxide pillar between the first and second vertical fins;
removing a portion of the oxide pillar to reduce a cross-sectional dimension of a lower end of the oxide pillar to define a recessed region of the oxide pillar;
wherein forming the first gate structure and the second gate structure includes depositing at least one metal gate material into the semiconductor substrate whereby the at least one gate material at least partially fills the recessed region of the oxide pillar to at least partially form the gate segments of the first and second metal gate structures.

19. A semiconductor device, comprising:
a substrate including first and second longitudinally spaced vertical fins extending vertically from the substrate;
first and second bottom source/drains beneath the first and second vertical fins, respectively;
a shallow trench isolation region within the substrate between the first and second bottom source/drains;
first and second top source/drains on the first and second spaced vertical fins, respectively; and
a first metal gate structure at least partially disposed about the first vertical fin;
a second metal gate structure at least partially disposed about the second vertical fin;
the first and second metal gate structures comprising respective a first and second gate segments each defining an L-shaped profile, the first and second gate segments being adjacent to each other; and
a single gate contact extending at least partially through the substrate between the first and second longitudinally spaced vertical fins and contacting both the first and second metal gate segments of the first and second metal gate structures.

20. The semiconductor device of

Assignees

• IBM

Inventors

• Xie Ruilong
• Xu Wenyu
• Anderson Brent Alan
• Liu Zuoguang

Classifications

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/0144

  Manufacturing their gate insulating layers · CPC title

• H10D84/0135

  Manufacturing their gate conductors · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title