Self-aligned replacement metal gate spacerless vertical field effect transistor

Patent metadata

Field	Value
Publication number	US-9882047-B2
Application number	US-201615012468-A
Country	US
Kind code	B2
Filing date	Feb 1, 2016
Priority date	Feb 1, 2016
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

A method of making a vertical field effect transistor includes forming a semiconductor nanowire that extends from a substrate surface. A first sacrificial layer is deposited over the substrate surface, and a second sacrificial layer is deposited over the first sacrificial layer such that each of the first and second sacrificial layers are formed peripheral to the nanowire. The second sacrificial layer is then patterned to form a dummy gate structure. Thereafter, the first sacrificial layer is removed and source and drain regions are deposited via epitaxy directly over respective portions of the nanowire.

First claim

What is claimed as new is:

1. A method of fabricating a vertical field effect transistor, comprising:
forming a semiconductor nanowire extending from a substrate surface;
depositing a first sacrificial layer over the substrate surface and surrounding the semiconductor nanowire, wherein the first sacrificial layer contacts a sidewall of a lower portion of the semiconductor nanowire and has a topmost surface that is below a topmost surface of the semiconductor nanowire;
depositing a second sacrificial layer over the first sacrificial layer and surrounding the semiconductor nanowire, wherein the second sacrificial layer contacts the sidewall of a middle portion of the semiconductor nanowire and has a topmost surface that is below the topmost surface of the semiconductor nanowire;
patterning the second sacrificial layer to form a sacrificial gate;
removing the first sacrificial layer to expose the sidewall of the lower portion of the semiconductor nanowire and to provide a gap between the sacrificial gate and the substrate surface;
epitaxially growing a bottom source/drain region in the gap and on the sidewall of the lower portion of the semiconductor nanowire, and a top source/drain region from an exposed surface of an upper portion of the semiconductor nanowire, wherein the bottom source/drain region is vertically spaced apart from the top source/drain region by the sacrificial gate; and
replacing the sacrificial gate with a gate stack comprising a gate dielectric layer and a conductive electrode to provide the vertical field effect transistor wherein a portion of the gate stack is positioned beneath the top source/drain region and above the bottom source/drain region.

2. The method of claim 1 , wherein the substrate surface comprises a dielectric material.

3. The method of claim 1 , wherein the first sacrificial layer comprises amorphous carbon.

4. The method of claim 1 , wherein the sacrificial gate comprises a dielectric material.

5. The method of claim 1 , wherein a contact area between the bottom source/drain region and the sacrificial gate is less than a contact area between the bottom source/drain region and the substrate surface.

6. The method of claim 1 , further comprising etching the top source/drain region to decrease a projected cross-sectional area thereof.

7. The method of claim 1 , further comprising depositing a dielectric layer over the sacrificial gate and etching vias in the dielectric layer to expose the sacrificial gate.

8. The method of claim 7 , further comprising etching the sacrificial gate through the vias.

9. The method of claim 1 , wherein the gate dielectric layer is deposited on the sidewall of the middle portion of the semiconductor nanowire and between the top and bottom source/drain regions.

10. The method of claim 1 , wherein the gate dielectric layer is deposited on the sidewall of the middle portion of the semiconductor nanowire, and the top and bottom source/drain regions.

11. The method of claim 1 , wherein a topmost surface of the top source/drain region is coplanar with a topmost surface of the gate stack.

Assignees

• IBM

Inventors

• Leobandung Effendi

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P14/3462

  Nanowires · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/42392

  Electricity · mapped topic

• H01L29/0676

  Electricity · mapped topic