Methods of forming vertical transistor devices with self-aligned replacement gate structures

Patent metadata

Field	Value
Publication number	US-9530863-B1
Application number	US-201615097574-A
Country	US
Kind code	B1
Filing date	Apr 13, 2016
Priority date	Apr 13, 2016
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

One illustrative method disclosed herein includes, among other things, forming a vertically oriented channel semiconductor structure, forming a layer of a bottom spacer material around the vertically oriented channel semiconductor structure and forming a sacrificial material layer above the layer of a bottom spacer material. In this example, the method further includes forming a sidewall spacer adjacent the vertically oriented channel semiconductor structure and above an upper surface of the sacrificial material layer, removing the sacrificial material layer so as to define a replacement gate cavity between a bottom surface of the sidewall spacer and the layer of a bottom spacer material, and forming a replacement gate structure in the replacement gate cavity.

First claim

What is claimed:

1. A method of forming a replacement gate structure on a vertical transistor device, the method comprising:
forming a vertically oriented channel semiconductor structure;
forming a layer of a bottom spacer material around said vertically oriented channel semiconductor structure;
forming a sacrificial material layer above said layer of said bottom spacer material, said sacrificial material layer having an upper surface;
forming a sidewall spacer adjacent said vertically oriented channel semiconductor structure and above said upper surface of said sacrificial material layer;
after forming said sidewall spacer, removing said sacrificial material layer so as to define a replacement gate cavity between a bottom surface of said sidewall spacer and said layer of said bottom spacer material; and
forming a replacement gate structure in said replacement gate cavity.

2. The method of claim 1 , wherein said sidewall spacer is formed on and in contact with a sidewall of said vertically oriented channel semiconductor structure and wherein said bottom surface of said sidewall spacer is formed on and in contact with said upper surface of said sacrificial material layer.

3. The method of claim 1 , wherein said layer of said bottom spacer material comprises silicon nitride, said sacrificial material layer comprises silicon dioxide, said sidewall spacer comprises SiOCN and said replacement gate structure comprises a high-k gate insulation layer, a work function adjusting metal-containing layer and a conductive fill layer.

4. The method of claim 1 , wherein an outer side surface of said replacement gate structure is substantially vertically aligned with an outer side surface of said sidewall spacer.

5. The method of claim 1 , wherein forming said replacement gate structure in said replacement gate cavity comprises depositing a plurality of gate material layers within said replacement gate cavity and performing at least one anisotropic etching process to remove portions of said plurality of gate material layers that are not covered by said sidewall spacer.

6. The method of claim 1 , wherein forming said replacement gate structure in said replacement gate cavity comprises:
performing a first conformal deposition process to form a layer of high-k insulating material on and in contact with sidewalls of said vertically oriented channel semiconductor structure within said replacement gate cavity;
performing a second conformal deposition process to form a metal-containing layer within said replacement gate cavity and on and in contact with said layer of high-k insulating material;
forming a conductive fill material within said replacement gate cavity; and
performing at least one anisotropic etching process to remove portions of said layer of high-k insulating material, said metal-containing layer and said conductive fill material that are not covered by said sidewall spacer.

7. The method of claim 1 , wherein said transistor device is one of an N-type device or a P-type device.

8. A method of forming a replacement gate structure on a vertical transistor device, the method comprising:
forming a vertically oriented channel semiconductor structure;
forming a layer of a bottom spacer material around said vertically oriented channel semiconductor structure;
forming a sacrificial material layer on and in contact with an upper surface of said layer of said bottom spacer material, said sacrificial material layer having an upper surface;
forming a sidewall spacer on and in contact with a sidewall of said vertically oriented channel semiconductor structure and on and in contact with said upper surface of said sacrificial material layer;
after forming said sidewall spacer, removing said sacrificial material layer so as to define a replacement gate cavity between a bottom surface of said sidewall spacer and an upper surface of said layer of said bottom spacer material; and
forming a replacement gate structure in said replacement gate cavity by depositing a plurality of gate material layers within said replacement gate cavity and performing at least one anisotropic etching process to remove portions of said plurality of gate material layers that are not covered by said sidewall spacer.

9. The method of claim 8 , wherein an outer side surface of said replacement gate structure is substantially vertically aligned with an outer side surface of said sidewall spacer.

10. The method of claim 8 , wherein depositing said plurality of gate material layers within said replacement gate cavity comprises:
performing a first conformal deposition process to form a layer of high-k insulating material on and in contact with sidewalls of said vertically oriented channel semiconductor structure within said replacement gate cavity;
performing a second conformal deposition process to form a metal-containing layer within said replacement gate cavity and on and in contact with said layer of high-k insulating material; and
forming a conductive fill material within said replacement gate cavity.

11. The method of claim 8 , wherein said transistor device is one of an N-type device or a P-type device.

12. A method of forming a vertical N-type transistor device and a vertical P-type transistor device structure, the method comprising:
forming a first and a second vertically oriented channel semiconductor structure for said N-type device and said P-type device, respectively;
forming a layer of a bottom spacer material around said first and second vertically oriented channel semiconductor structures;
forming a sacrificial material layer above said layer of said bottom spacer material and around said first and second vertically oriented channel semiconductor structures, said sacrificial material layer having an upper surface;
forming a first sidewall spacer and a second sidewall spacer adjacent said first and second vertically oriented channel semiconductor structures, respectively, and above said upper surface of said sacrificial material layer;
after forming said first and second sidewall spacers, removing said sacrificial material layer so as to define a first replacement gate cavity for said N-type device between a bottom surface of said first sidewall spacer and said layer of said bottom spacer material and a second replacement gate cavity for said P-type device between a bottom surface of said second sidewall spacer and said layer of said bottom spacer material; and
forming a first replacement gate structure in said first replacement gate cavity and a second replacement gate structure in said second replacement gate cavity, wherein said first and second replacement gate structures are conductively coupled to one another by a layer of conductive material that is present in both said first and second replacement gate structures.

13. The method of claim 12 , wherein said first and second sidewall spacers are formed on and in contact with a sidewall of said first and second vertically oriented channel semiconductor structures, respectively, and wherein a bottom surface of said first sidewall spacer and a bottom surface of said second sidewall spacer is formed on and in contact with said upper surface of said sacrificial material layer.

14. The method of claim 12 , wherein said layer of said bottom spacer material comprises silicon nitride, said sacrificial material layer comprises silicon dioxide and said first and second sidewall spacers comprise SiOCN.

15. The method of claim 12 , wherein said first and second replacement gate structures are comprised of the same material.

16. The method of claim 12 , wherein said first and

Assignees

• Globalfoundries Inc

Inventors

• Zhang John H
• Radens Carl
• Bentley Steven J
• Cohen Brian A
• Lim Kwan-Yong

Classifications

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10D30/025

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title

• H10D64/017 Primary

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H01L29/66545 Primary

  Electricity · mapped topic