Spacer-confined epitaxial growth

Patent metadata

Field	Value
Publication number	US-10978573-B2
Application number	US-201916504739-A
Country	US
Kind code	B2
Filing date	Jul 8, 2019
Priority date	Jul 8, 2019
Publication date	Apr 13, 2021
Grant date	Apr 13, 2021

Abstract

Semiconductor devices and methods of forming the same include forming a dummy gate on a stack of alternating channel layers and sacrificial layers. A spacer layer is formed over the dummy gate and the stack. Portions of the spacer layer on horizontal surfaces of the stack are etched away to form vertical spacers. Exposed portions of the stack are etched away. Semiconductor material is grown from exposed sidewalls of remaining channel layers to form source and drain structures that are constrained in lateral dimensions by the vertical spacers.

First claim

What is claimed is:

1. A method for forming a semiconductor device, comprising:
forming a dummy gate on a stack of alternating channel layers and sacrificial layers;
forming a spacer layer over the dummy gate and the stack;
etching away portions of the spacer layer on horizontal surfaces of the stack to form vertical spacers;
etching away exposed portions of the stack after etching away the portions of the spacer layer; and
growing semiconductor material from exposed sidewalls of remaining channel layers to form source and drain structures that are constrained in lateral dimensions by the vertical spacers.

2. The method of claim 1 , wherein etching away the portions of the spacer layer comprises an anisotropic etch that preferentially removes material in a vertical direction.

3. The method of claim 1 , wherein etching away portions of the stack comprises an anisotropic etch that selectively removes material from the stack in a vertical direction, leaving behind a channel portion of the stack under the dummy gate and the vertical spacers.

4. The method of claim 3 , further comprising horizontally recessing the sacrificial layers in the channel portion of the stack relative to sidewalls of the channel layers of the channel portion of the stack.

5. The method of claim 4 , further comprising forming inner spacers, on sidewalls of the recessed sacrificial layers, that cover exposed top and bottom surfaces of the channel layers in the channel portion of the stack.

6. The method of claim 1 , wherein growing semiconductor material comprises epitaxial growth of semiconductor material from exposed vertical surfaces of the channel layers under the dummy gates.

7. The method of claim 1 , further comprising an interlayer dielectric formed over the source and drain structures and over the vertical spacers.

8. The method of claim 7 , wherein the interlayer dielectric is formed from a distinct material as compared to a material of the vertical spacers.

9. A method for forming a semiconductor device, comprising:
forming a dummy gate on a stack of alternating channel layers and sacrificial layers that are formed from distinct semiconductor materials;
forming a spacer layer over the dummy gate and the stack;
etching away portions of the spacer layer on horizontal surfaces of the stack to form vertical spacers;
etching away exposed portions of the stack after etching away the portions of the spacer layer;
epitaxially growing semiconductor material from exposed vertical sidewall surfaces of remaining channel layers of the stack to form source and drain structures that are constrained in lateral dimensions by the vertical spacers; and
forming an interlayer dielectric over the source and drain structures and over the vertical spacers from a distinct material as compared to material of the vertical spacers.

10. The method of claim 9 , wherein etching away the portions of the spacer layer comprises an anisotropic etch that preferentially removes material in a vertical direction.

11. The method of claim 9 , wherein etching away portions of the stack comprises an anisotropic etch that selectively removes material from the stack in a vertical direction, leaving behind a channel portion of the stack under the dummy gate and the vertical spacers.

12. The method of claim 11 , further comprising horizontally recessing the sacrificial layers in the channel portion of the stack relative to sidewalls of the channel layers of the channel portion of the stack.

13. The method of claim 12 , further comprising forming inner spacers, on sidewalls of the recessed sacrificial layers, that cover exposed top and bottom surfaces of the channel layers in the channel portion of the stack.

14. A semiconductor device, comprising:
a plurality of vertically arranged channel layers;
a source structure and a drain structure at respective ends of the vertically arranged channel layers;
a vertical sidewall spacer formed on sidewalls of the source structure and the drain structure, having a bottom surface that is at a same height as a bottom surface of the source structure and the drain structure; and
a gate stack formed over, around, and between the vertically arranged channel layers.

15. The semiconductor device of claim 14 , wherein the source structure and drain structure are epitaxially grown from vertical side surfaces of the vertically arranged channel layers to form a continuous crystal structure therewith.

16. The semiconductor device of claim 15 , wherein the vertical sidewall spacer confines the source structure and the drain structure to a horizontal dimension that is smaller than would have resulted from unconstrained epitaxial growth and in alignment with a channel width.

17. The semiconductor device of claim 14 , further comprising an interlayer dielectric formed over the source structure and drain structure and over the vertical sidewall spacer.

18. The semiconductor device of claim 17 , wherein the interlayer dielectric is formed from a distinct material as compared to a material of the vertical sidewall spacer.

19. The semiconductor device of claim 14 , further comprising inner spacers formed between respective vertically adjacent pairs of the vertically arranged channel layers.

20. The semiconductor device of claim 14 , wherein the source structure and the drain structure are each bounded on three vertical sides by the vertical sidewall spacer.

Assignees

• IBM

Inventors

• Yogendra Karthik
• Rahman Ardasheir
• Robison Robert
• Carr Adra

Classifications

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0147

  Manufacturing their gate sidewall spacers · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D64/015

  removing at least parts of gate spacers, e.g. disposable spacers · CPC title