Semiconductor packages with pass-through clock traces and associated systems and methods

Patent metadata

Field	Value
Publication number	US-10978426-B2
Application number	US-201916512591-A
Country	US
Kind code	B2
Filing date	Jul 16, 2019
Priority date	Dec 31, 2018
Publication date	Apr 13, 2021
Grant date	Apr 13, 2021

Abstract

Semiconductor packages with pass-through clock traces and associated devices, systems, and methods are disclosed herein. In one embodiment, a semiconductor device includes a package substrate including a first surface having a plurality of substrate contacts, a first semiconductor die having a lower surface attached to the first surface of the package substrate, and a second semiconductor die stacked on top of the first semiconductor die. The first semiconductor die includes an upper surface including a first conductive contact, and the second semiconductor die includes a second conductive contact. A first electrical connector electrically couples a first one of the plurality of substrate contacts to the first and second conductive contacts, and a second electrical connector electrically couples a second one of the plurality of substrate contacts to the first and second conductive contacts.

First claim

We claim:

1. A semiconductor device, comprising:
a package substrate including a first surface having a plurality of substrate contacts;
a first semiconductor die having a lower surface attached to the first surface of the package substrate and an upper surface including a first conductive contact;
a second semiconductor die stacked on top of the first semiconductor die and including a second conductive contact;
a first electrical connector electrically coupling a first one of the plurality of substrate contacts to the first and second conductive contacts; and
a second electrical connector electrically coupling a second one of the plurality of substrate contacts to the first and second conductive contacts,
wherein the first and second ones of the plurality of substrate contacts are disposed adjacent different edges of the first semiconductor die, and wherein the package substrate is electrically coupled to the first and second semiconductor dies via (a) the first conductive contact and/or the second conductive contact and (b) the first and second electrical connectors such that a clock signal transmitted from the package substrate to the first and second semiconductor dies via one of the first and second electrical connectors returns to the package substrate via the other of the first and second electrical connectors.

2. The semiconductor device of claim 1 , wherein at least one of the first and second electrical connectors includes a wire bond.

3. The semiconductor device of claim 1 , wherein at least one of the first and second electrical connectors includes a through substrate via (TSV), wherein the semiconductor device further comprises a third electrical connector and/or a fourth electrical connector electrically coupling the TSV of the first electrical connector and/or the TSV of the second electrical connector, respectively, to the first one and/or the second one, respectively, of the plurality of substrate contacts, and wherein the first and second ones of the plurality of substrate contacts are disposed under the first semiconductor die.

4. The semiconductor device of claim 3 , wherein the first semiconductor die includes the TSV of the first electrical connector and/or the TSV of the second electrical connector.

5. The semiconductor device of claim 1 , wherein the first and second semiconductor dies are stacked in a face-to-face orientation on the package substrate.

6. The semiconductor device of claim 1 , wherein the first semiconductor die is attached to the package substrate such that a face of the first semiconductor die is directed toward the package substrate.

7. The semiconductor device of claim 6 , wherein the first semiconductor die is attached to the package substrate via a direct contact attachment (DCA).

8. The semiconductor device of claim 6 , wherein the second semiconductor die is stacked on the first semiconductor die such that a face of the second semiconductor die is directed toward the first semiconductor die and the package substrate.

9. The semiconductor device of claim 1 , wherein the semiconductor device is a dynamic random-access memory (DRAM) semiconductor device.

10. The semiconductor device of claim 1 , further comprising—
a printed circuit board (PCB) having a plurality of electrical contacts; and
two electrical connectors electrically coupled to substrate contacts of a second surface of the package substrate opposite the first surface, wherein a first electrical connector of the two electrical connectors is configured to electrically couple the first one of the plurality of substrate contacts of the first surface of the package substrate to a first one of the plurality of electrical contacts of the PCB, and wherein a second electrical connector of the two electrical connectors is configured to electrically couple the second one of the plurality of substrate contacts of the first surface of the package substrate to a second one of the plurality of electrical contacts of the PCB.

11. The semiconductor device of claim 10 , wherein the PCB includes a clock trace electrically coupled to the first one and the second one of the plurality of electrical contacts of the PCB such that the clock signal is transmitted from the clock trace to the first and second semiconductor dies via the one of the first and second electrical connectors and is returned to the clock trace via the other of the first and second electrical connectors.

12. A method of manufacturing a semiconductor device, the method comprising:
forming a package substrate, the package substrate including a first surface having a plurality of substrate contacts;
disposing a first semiconductor die over the first surface of the package substrate, the first semiconductor die having a lower surface attached to the first surface of the package substrate and an upper surface including a first conductive contact;
disposing a second semiconductor die over the first semiconductor die, the second semiconductor die including a second conductive contact; and
electrically coupling the package substrate to the first and second semiconductor dies via (a) the first conductive contact and/or the second conductive contact and (b) first and second electrical connectors such that a clock signal transmitted from the package substrate to the first and second semiconductor dies via one of the first and second electrical connectors returns to the package substrate via the other of the first and second electrical connectors,
wherein electrically coupling the package substrate to the first and second semiconductor dies includes:
forming the first electrical connector, the first electrical connector coupling a first one of the plurality of substrate contacts to the first and second conductive contacts; and
forming the second electrical connector, the second electrical connector coupling a second one of the plurality of substrate contacts to the first and second conductive contacts, and

wherein the first and second ones of the plurality of substrate contacts are disposed adjacent different edges of the first semiconductor die.

13. The method of claim 12 , wherein at least one of the first and second electrical connectors includes a wire bond.

14. The method of claim 12 , wherein at least one of the first and second electrical connectors includes a through substrate via (TSV), wherein electrically coupling the package substrate to the first and second semiconductor dies further includes forming a third electrical connector and/or a fourth electrical connector electrically coupling the TSV of the first electrical connector and/or the TSV of the second electrical connector, respectively, to the first one and/or the second one, respectively, of the plurality of substrate contacts, and wherein the first and second ones of the plurality of substrate contacts are disposed under the first semiconductor die.

15. The method of claim 14 , wherein the first semiconductor die includes the TSV of the first electrical connector and/or the TSV of the second electrical connector.

16. The method of claim 12 , wherein disposing the first semiconductor die includes disposing the first semiconductor die such that a face of the first semiconductor die is directed away from the package substrate, and wherein disposing the second semiconductor die includes disposing the second semiconductor die over the first semiconductor die such that a face of the second semiconductor die is directed toward the face of the first semiconductor die.

17. The method of claim 12 , wherein disposing the first semiconductor die includes disposing the fir

Assignees

• Micron Technology Inc

Inventors

• Kinsley Thomas H
• Pax George E

Classifications

• H10W90/794

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W72/07554

  changes in dispositions · CPC title