Systems, methods, and apparatuses for stacked memory

Patent metadata

Field	Value
Publication number	US-9886343-B2
Application number	US-201514622776-A
Country	US
Kind code	B2
Filing date	Feb 13, 2015
Priority date	Dec 31, 2009
Publication date	Feb 6, 2018
Grant date	Feb 6, 2018

Abstract

Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

First claim

What is claimed is:

1. A memory device comprising:
a logic die, the logic die including logic to support an input/output (IO) interface and packet processing operations; and
a plurality of memory dies stacked on the logic die, the memory dies each including memory die portions, each memory die portion including a memory array and IO logic;
wherein the logic die further includes multiple logic portions, wherein each logic portion is coupled by way of a through silicon via to vertically aligned ones of the memory die portions, each logic portion comprises the following:
built-in self test (BIST) logic to provide testing of the memory arrays of the plurality of memory dies, and
dynamic error workaround logic to provide capabilities to handle soft errors and hard errors appearing in the memory arrays of the one or more memory die portions of the plurality of memory dies, the dynamic error workaround logic of the logic die including an error checking and correction (ECC) logic to check for errors appearing in memory and a redundancy control logic, wherein handling soft errors and hard errors includes the dynamic error workaround logic of the logic die to handle soft errors in a first manner, including utilizing the ECC logic of the logic die to attempt to correct soft errors, and to handle hard errors in a second manner, including utilizing the redundancy control logic of the logic die to address hard errors for at least some of the one or more memory die portions.

2. The memory device of claim 1 , wherein the ECC logic incorporates a BCH (Bose, Ray-Chaudhuri, and Hocquenghem) error correcting code.

3. The memory device of claim 1 , wherein addressing hard errors utilizing the redundancy control logic includes the redundancy control logic to shut down one or more parts of a memory array of a memory die portion in response to certain test results.

4. The memory device of claim 3 , wherein a shutdown of a part of a memory array by the redundancy control logic of the dynamic error workaround logic is permanent.

5. The memory device of claim 3 , wherein shutting down one or more parts of a memory array by the redundancy control logic of the dynamic error workaround logic includes shutting down a column of memory.

6. The memory device of claim 3 , wherein the redundancy control logic of the dynamic error workaround logic includes multiplexer logic, the multiplexer logic to keep track of parts of memory for shut down in a memory array of the one or more memory die portions of the plurality of memory dies.

7. The memory device of claim 1 , wherein the dynamic error workaround logic of the logic die further includes cache line disable logic to disable memory pages or rows.

8. The memory device of claim 7 , wherein the logic die further includes a tag cache.

9. The memory device of claim 1 , wherein the logic of the logic die further includes IO logic, the IO logic to support the IO interface and packet processing logic to support the packet processing operation.

10. The memory device of claim 1 , wherein the memory device provides a first level of memory in a computing system having two or more levels of memory, the computing system to include a second level of memory external to the memory device, the second level of memory having a plurality of memory blocks.

11. The memory device of claim 1 , wherein the logic die further includes one or more of:
an adaptive power logic operable to modify power delivered to the memory dies; and
adaptive refresh logic operable to modify time between memory refreshes.

12. A system comprising:
a processor; and
a memory device coupled with the processor via an interconnect, the memory device including:
a logic die, the logic die including logic to support an input/output (IO) interface with the processor and packet processing operations, and
a plurality of memory dies stacked on the logic die, the memory dies each including memory die portions, each memory die portion including a memory array and IO logic;

wherein the logic die further includes multiple logic portions, wherein each logic portion is coupled by way of a through silicon via to vertically aligned ones of the memory die portions, each logic portion comprises the following:
built-in self test (BIST) logic to provide testing of the memory arrays of the memory dies, and
dynamic error workaround logic to provide capabilities to handle soft errors and hard errors appearing in the memory arrays of the one or more memory die portions of the plurality of memory dies, the dynamic error workaround logic of the logic die including an error checking and correction (ECC) logic to check for errors appearing in memory and a redundancy control logic, wherein handling soft errors and hard errors includes the dynamic error workaround logic of the logic die to handle soft errors in a first manner, including utilizing the ECC logic of the logic die to attempt to correct soft errors, and to handle hard errors in a second manner, including utilizing the redundancy control logic of the logic die to address hard errors for at least some of the one or more memory die portions.

13. The system of claim 12 , wherein addressing hard errors utilizing the redundancy control logic includes the redundancy control logic to shut down one or more parts of a memory array of a memory die portion in response to certain test results.

14. The system of claim 13 , wherein a shutdown of a part of a memory array by the redundancy control logic of the dynamic error workaround logic is permanent.

15. The system of claim 13 , wherein the redundancy control logic of the dynamic error workaround logic includes multiplexer logic to keep track of parts of memory for shut down in a memory array of the one or more memory die portions of the plurality of memory dies.

16. The system of claim 12 , further comprising:
a network interface communicatively coupled to the processor.

17. An apparatus comprising:
a logic die, the logic die including logic to support an input/output (IO) interface and packet processing operations; and
a plurality of memory dies stacked on the logic die, the plurality of memory dies each including multiple memory tiles, wherein vertically aligned ones of the memory dies across the plurality of memory dies form a respective column of memory tiles, each memory tile of a column of memory tiles including a memory array and IO logic;
wherein the logic die further includes multiple logic portions, wherein each logic portion is coupled by way of a through silicon via to a respective column of memory tiles, each logic portion comprises the following:
built-in self test (BIST) logic to provide testing of the memory arrays of the plurality of memory dies, and
dynamic error workaround logic to provide capabilities to handle soft errors and hard errors appearing in the memory arrays of the memory tiles of the plurality of memory dies, the dynamic error workaround logic of the logic die including an error checking and correction (ECC) logic to check for errors appearing in memory and a redundancy control logic, wherein handling soft errors and hard errors includes the dynamic error workaround logic of the logic die to handle soft errors in a first manner, including utilizing the ECC logic of the logic die to attempt to correct soft errors, and to handle hard errors in a second manner, including utilizing the redundancy control logic of the logic die to address hard errors for at least some of the one or more memory die portions.

18. The apparatus of claim 17 , wherein addressing hard errors utilizing

Assignees

• Intel Corp

Inventors

• Casper Bryan K
• Mooney Stephen R
• Dunning David
• Mansuri Mozhgan
• Jaussi James E

Classifications

• H10W90/722

  between stacked chips · CPC title

• G11C29/12

  Built-in arrangements for testing, e.g. built-in self testing [BIST] {or interconnection details} · CPC title

• H03M13/15

  Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes (H03M13/17 takes precedence) · CPC title

• H03M13/152

  Bose-Chaudhuri-Hocquenghem [BCH] codes · CPC title

• G11C5/02 Primary

  Disposition of storage elements, e.g. in the form of a matrix array · CPC title