Semiconductor die assembly

Patent metadata

Field	Value
Publication number	US-9601374-B2
Application number	US-201514669780-A
Country	US
Kind code	B2
Filing date	Mar 26, 2015
Priority date	Mar 26, 2015
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

A semiconductor die assembly having a solderball wirebonded to a substrate. As an example, the semiconductor die assembly may include the solderball attached to a bond pad on a face surface of a memory die. A non-face surface of the memory die can be attached to the substrate. A wire can be wirebonded to the solderball at a first end of the wire and connected to the substrate at a second end of the wire.

First claim

What is claimed is:

1. A semiconductor die assembly, comprising:
an interconnect structure comprised of a first type of metal attached to a bond pad on a face surface of a memory die;
a non-face surface of the memory die attached to a substrate; and
a wire comprised of a second type of metal wirebonded to the interconnect structure at a first end of the wire to form a reflowed intermetallic layer and connected to the substrate at a second end of the wire.

2. The semiconductor die assembly of claim 1 , comprising an additional memory die, wherein the additional memory die comprises:
an additional bond pad; and
an additional interconnect structure bonded to the first end of the wire.

3. The semiconductor die assembly of claim 2 , wherein the memory die and the additional memory die are configured in a face-to-face configuration.

4. The semiconductor die assembly of claim 3 , wherein an interface between the face surface of the memory die and a face surface of the additional memory die does not include a redistributed layer (RDL).

5. The semiconductor die assembly of claim 1 , wherein the wire is wirebonded to the bond pad of an additional memory die and the interconnect structure is wirebonded to the wire.

6. The semiconductor die assembly of claim 1 , wherein the wire is at least one of a gold wire, a silver wire, a copper wire, and an alloy composition of at least two of gold, silver, and copper.

7. The semiconductor die assembly of claim 1 , wherein the wire is wirebonded to the interconnect structure using an intermetallic layer between the wire and solder of the interconnect structure.

8. The semiconductor die assembly of claim 1 , wherein the wire is comprised of gold (Au) and the interconnect structure is comprised of tin (Sn), silver (Ag), and copper (Cu).

9. A semiconductor die assembly, comprising:
a first memory die including a first bond pad wirebonded to a wire comprised of a first type of metal;
a second memory die including a second bond pad connected to an interconnect structure comprised of a second type of metal to form a reflowed intermetallic layer; and
a substrate;
wherein the interconnect structure is bonded to the wire and the wire is connected to the substrate.

10. The semiconductor die assembly of claim 9 , wherein the first memory die and the second memory die are in a face-to-face configuration.

11. The semiconductor die assembly of claim 9 , wherein an additional interconnect structure is connected to the first bond pad and the additional interconnect structure is bonded to the wire.

12. The semiconductor die assembly of claim 9 , wherein the interconnect structure of the second memory die comprises a gold stud bump.

13. The semiconductor die assembly of claim 9 , wherein the interconnect structure of the second memory die comprises a solderball.

14. The semiconductor die assembly of claim 13 , wherein the solderball comprises an electroplated structure.

15. The semiconductor die assembly of claim 14 , wherein the solderball further comprises an intermetallic nickel layer.

16. The semiconductor die assembly of claim 15 , wherein the tin-silver layer is wirebonded to the wire.

17. A method, comprising:
forming a solderball on a face surface of a first memory die;
wirebonding a first end of a wire to the solderball and a second end of the wire to a substrate, wherein the wire is comprised of a different metal than the solderball and the wire and the solderball form a reflowed intermetallic layer; and
attaching a second memory die in a flipped orientation such that a face surface of the second memory die faces the face surface of the first memory die.

18. The method of claim 17 , wherein the first memory die and the second memory die are connected to the substrate without using a redistributed layer.

19. The method of claim 17 , wherein the solderball on the face surface of the first memory die is on a bond pad of the first memory die.

20. The method of claim 17 , wherein attaching the second memory die comprises wirebonding a solderball attached to a bond pad on the face surface of the second memory die to the wire.

21. The method of claim 17 , comprising attaching a non-face surface of the first memory die to the substrate.

22. The method of claim 17 , comprising reflowing the first memory die attached to the second memory die to form an intermetallic layer between the wire and the solderball.

23. The method of claim 17 , comprising creating the first memory die by singulating a wafer.

24. The method of claim 23 , wherein the solderball is formed on the wafer prior to singulating the wafer to create the first memory die.

25. The method of claim 17 , wherein attaching the second memory die to the first memory die comprises:
flipping the second memory die; and
dipping the second memory die in flux.

26. The method of claim 25 , wherein attaching the second memory die to the first memory die comprises:
aligning the second memory die in a face-to-face configuration with the first memory die; and
placing the second memory die onto the first memory die.

27. A method, comprising:
forming a first solderball on a face surface of a first memory die;
wirebonding a first end of a first wire to the first solderball and a second end of the first wire to a substrate;
attaching a second memory die in a flipped orientation such that a face surface of the second memory die faces the face surface of the first memory die;
forming a second solderball on a face surface of a third memory die;
wirebonding a first end of a second wire to the second solderball and a second end of the second wire to the substrate; and
attaching a fourth memory die in a flipped orientation with respect to the third memory die such that a face surface of the fourth memory die faces the face surface of the third memory die; and
reflowing the first memory die, the second memory die, the third memory die, and the fourth memory die such that the first wire and the first solderball form a first reflowed intermetallic layer and the second wire and the second solderball form a second reflowed intermetallic layer.

Assignees

• Micron Technology Inc

Inventors

• Fay Owen R
• Foster Liana

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/271

  the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title