Semiconductor package having a redistribution line structure

Patent metadata

Field	Value
Publication number	US-10115708-B2
Application number	US-201715443509-A
Country	US
Kind code	B2
Filing date	Feb 27, 2017
Priority date	Nov 16, 2016
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

A semiconductor package may include a first semiconductor chip having first bonding pads on a first active surface. The semiconductor package may include a second semiconductor chip having second bonding pads which are arranged on a second active surface. The first and second semiconductor chips are stacked such that the first and second active surfaces face each other.

First claim

What is claimed is:

1. A semiconductor package comprising:
a first semiconductor chip having first bonding pads which are arranged in two rows on a middle portion of a first active surface;
a second semiconductor chip having substantially the same size as the first semiconductor chip, and having second bonding pads which are arranged in two rows on a middle portion of a second active surface;
redistribution lines formed on the first active surface, and corresponding to the first bonding pads, respectively, the redistribution lines each having a redistribution line pad, a wire bonding pad, and coupling lines electrically coupling the redistribution line pad, the wire bonding pad and the corresponding first bonding pad; and
bumps formed on the second bonding pads of the second semiconductor chip, respectively,
wherein the location of the second bonding pads in relation to the second semiconductor chip is the same as the location of the corresponding first bonding pads in relation to the first semiconductor chip,
wherein the first semiconductor chip and the second semiconductor chip are stacked such that the first active surface and the second active surface face each other, and are disposed to be offset from each other, and
wherein the bumps are bonded to the redistribution line pads of the redistribution lines, respectively.

2. The semiconductor package according to claim 1 ,
wherein the redistribution lines comprise:
a first redistribution line coupled with one side first bonding pad of the first bonding pads arranged in two rows, and extending toward one side edge of the first semiconductor chip; and
a second redistribution line coupled with an other side first bonding pad of the first bonding pads arranged in two rows, and extending toward an other side edge of the first semiconductor chip,
wherein the second bonding pads of the second semiconductor chip include one side second bonding pad and an other side second bonding pad, and
wherein the bumps include one side bump which is formed on the one side second bonding pad and an other side bump which is formed on the other side second bonding pad.

3. The semiconductor package according to claim 2 ,
wherein the first redistribution line comprises:
a first wire bonding pad disposed adjacent to the one side edge;
a first redistribution line pad disposed adjacent to the other side first bonding pad between the other side first bonding pad and the other side edge; and
a first coupling line coupling the first wire bonding pad and the first redistribution line pad via the one side first bonding pad, and
wherein the second redistribution line comprises:
a second wire bonding pad disposed adjacent to the other side edge;
a second redistribution line pad disposed between the one side first bonding pad and the other side first bonding pad; and
a second coupling line coupling the second wire bonding pad and the second redistribution line pad via the other side first bonding pad.

4. The semiconductor package according to claim 3 , wherein the one side and the other side first bonding pads and the first and second redistribution line pads are disposed by being aligned in a line on the first active surface of the first semiconductor chip.

5. The semiconductor package according to claim 3 , wherein a pitch between the one side first bonding pad and the second redistribution line pad is the same as an offset distance between the first semiconductor chip and the second semiconductor chip.

6. The semiconductor package according to claim 3 ,
wherein the one side second bonding pad is electrically coupled with the second redistribution line pad through the one side bump, and
wherein the other side second bonding pad is electrically coupled with the first redistribution line pad through the other side bump.

7. The semiconductor package according to claim 6 ,
wherein the one side first bonding pad of the first semiconductor chip and the other side second bonding pad of the second semiconductor chip are electrically coupled with each other through the other side bump which is formed on the other side second bonding pad and a first redistribution line pad which is electrically coupled with the other side bump and is coupled with the one side first bonding pad, and
wherein the other side first bonding pad of the first semiconductor chip and the one side second bonding pad of the second semiconductor chip are electrically coupled with each other through the one side bump which is formed on the one side second bonding pad and a second redistribution line pad which is electrically coupled with the one side bump and is coupled with the other side first bonding pad.

8. The semiconductor package according to claim 2 ,
wherein the first redistribution line comprises:
a first wire bonding pad disposed adjacent to the one side edge;
a first redistribution line pad disposed adjacent to the other side first bonding pad between the other side first bonding pad and the other side edge; and
a first coupling line coupling the first wire bonding pad and the first redistribution line pad via the one side first bonding pad, and
wherein the second redistribution line comprises:
a second wire bonding pad disposed adjacent to the other side edge;
a second redistribution line pad disposed between the other side first bonding pad and the first redistribution line pad; and
a second coupling line coupling the second wire bonding pad and the other side first bonding pad via the second redistribution line pad.

9. The semiconductor package according to claim 8 , wherein the one side and the other side first bonding pads and the first and second redistribution line pads are disposed by being aligned in a line.

10. The semiconductor package according to claim 8 , wherein a pitch between the first side first bonding pad and the second redistribution line pad is the same as an offset distance between the first semiconductor chip and the second semiconductor chip.

11. The semiconductor package according to claim 8 ,
wherein the one side second bonding pad of the second semiconductor chip is electrically coupled with the second redistribution line pad of the first semiconductor chip through the one side bump, and
wherein the other side second bonding pad of the second semiconductor chip is electrically coupled with the first redistribution line pad of the first semiconductor chip through the other side bump.

12. The semiconductor package according to claim 11 ,
wherein the one side first bonding pad of the first semiconductor chip and the other side second bonding pad of the second semiconductor chip are electrically coupled with each other through the other side bump which is formed on the other side second bonding pad and a first redistribution line pad which is electrically coupled with the other side bump and is coupled with the one side first bonding pad, and
wherein the other side first bonding pad of the first semiconductor chip and the one side second bonding pad of the second semiconductor chip are electrically coupled with each other through the one side bump which is formed on the one side second bonding pad and a second redistribution line pad which is electrically coupled with the one side bump and is coupled with the other side first bonding pad.

13. The semiconductor package according to claim 1 , wherein the first semiconductor chip further has a first redistribution line insulation layer which is formed over the first active surface to expose the first bonding pads, and a second redistribution line insulation layer which is formed on the first redistribution line insulation layer to cover the redistri

Assignees

• Sk Hynix Inc

Inventors

• Eom Ju Il
• Lee Jae Hoon
• Lim Sang Joon

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/721

  of bump connectors · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title