Interface charge reduction for SiGe surface

Patent metadata

Field	Value
Publication number	US-10971626-B2
Application number	US-201916502685-A
Country	US
Kind code	B2
Filing date	Jul 3, 2019
Priority date	Jul 28, 2017
Publication date	Apr 6, 2021
Grant date	Apr 6, 2021

Abstract

Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.

First claim

What is claimed is:

1. A field effect transistor (FET) device, comprising:
a substrate;
an epitaxial silicon germanium (SiGe) channel material disposed on the substrate;
a thin continuous silicon (Si) layer formed on a surface of the SiGe channel material, wherein the thin continuous Si layer is less than 5 monolayers thick, wherein the SiGe channel material comprises planar surfaces and faceted surfaces, wherein the Si layer has a thickness T 1 over the planar surfaces and a thickness T 2 over the faceted surfaces, and wherein T 1 >T 2 ; and
a gate stack disposed on the SiGe channel material, wherein the gate stack comprises a gate dielectric disposed on the SiGe channel material over the thin continuous Si layer and a gate conductor on the gate dielectric, and wherein the thin continuous Si layer passivates an interface between the SiGe channel material and the gate dielectric.

2. The FET device of claim 1 , wherein a surface of the SiGe channel material comprises a chemically doped n-type dopant selected from the group consisting of: phosphorous, arsenic, bismuth, and combinations thereof.

3. The FET device of claim 1 , wherein the SiGe channel material and the substrate are patterned into at least one fin.

4. The FET device of claim 3 , wherein each fin has a top portion comprising the SiGe material and a bottom portion comprising the substrate.

5. The FET device of claim 4 , further comprising:
a shallow trench isolation (STI) oxide disposed around the bottom portion of each fin.

6. The FET device of claim 1 , wherein the SiGe channel material contains from about 15% to about 40% germanium (Ge) and ranges therebetween.

7. The FET device of claim 1 , wherein the SiGe channel material contains from about 15% to about 25% Ge and ranges therebetween.

8. The FET device of claim 1 , wherein the substrate comprises a crystalline semiconductor material.

9. The FET device of claim 8 , wherein the crystalline semiconductor material is selected from the group consisting of: crystalline Si, crystalline SiGe, a crystalline III-V material, a crystalline II-VI material, and combinations thereof.

10. The FET device of claim 1 , wherein the substrate comprises exposed crystallographic surface orientations on which the SiGe channel material is disposed.

11. A FET device, comprising:
a substrate;
an epitaxial SiGe channel material disposed on the substrate, wherein the SiGe channel material and the substrate are patterned into at least one fin, and wherein each fin has a top portion comprising the SiGe material and a bottom portion comprising the substrate;
a thin continuous Si layer formed on a surface of the SiGe channel material, wherein the thin continuous Si layer is less than 5 monolayers thick, wherein the SiGe channel material comprises planar surfaces and faceted surfaces, wherein the Si layer has a thickness T 1 over the planar surfaces and a thickness T 2 over the faceted surfaces, and wherein T 1 >T 2 ; and
a gate stack disposed on the SiGe channel material, wherein the gate stack comprises a gate dielectric disposed on the SiGe channel material over the thin continuous Si layer and a gate conductor on the gate dielectric, and wherein the thin continuous Si layer passivates an interface between the SiGe channel material and the gate dielectric.

12. The FET device of claim 11 , wherein a surface of the SiGe channel material comprises a chemically doped n-type dopant selected from the group consisting of: phosphorous, arsenic, bismuth, and combinations thereof.

13. The FET device of claim 11 , further comprising:
an STI oxide disposed around the bottom portion of each fin.

14. The FET device of claim 11 , wherein the SiGe channel material contains from about 15% to about 40% Ge and ranges therebetween.

15. The FET device of claim 11 , wherein the substrate comprises a crystalline semiconductor material.

16. The FET device of claim 15 , wherein the crystalline semiconductor material is selected from the group consisting of: crystalline Si, crystalline SiGe, a crystalline III-V material, a crystalline II-VI material, and combinations thereof.

Assignees

• IBM

Inventors

• Sadana Devendra
• Guo Dechao
• De Souza Joel P
• Bao Ruqiang
• Bedell Stephen W
• Mochizuki Shogo
• Tsutsui Gen
• Jagannathan Hemanth
• Hopstaken Marinus

Classifications

• H10P14/6903

  containing silicon · CPC title

• H10P14/6506

  Formation of intermediate materials · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3258

  Crystal orientation · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title