Transistor contacts and methods of forming the same
US-2024395871-A1 · Nov 28, 2024 · US
US2016190286A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016190286-A1 |
| Application number | US-201414586313-A |
| Country | US |
| Kind code | A1 |
| Filing date | Dec 30, 2014 |
| Priority date | Dec 30, 2014 |
| Publication date | Jun 30, 2016 |
| Grant date | — |
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The present disclosure provides a method forming a semiconductor device in accordance with some embodiments. The method includes receiving a substrate having a fin protruding through the substrate, wherein the fin is formed of a first semiconductor material, exposing the substrate in an environment including hydrogen radicals, thereby passivating the protruded fin using the hydrogen radicals, and epitaxially growing a cap layer of a second semiconductor material to cover the protruded fin.
Opening claim text (preview).
What is claimed is: 1 . A method, comprising: receiving a substrate having a fin protruding through the substrate, wherein the fin is formed of a first semiconductor material; exposing the substrate in an environment including hydrogen radicals, thereby passivating the protruded fin using the hydrogen radicals; and epitaxially growing a cap layer of a second semiconductor material to cover the protruded fin. 2 . The method of claim 1 , wherein the first semiconductor material includes a material selected from the group consisting of germanium, germanium silicon, and germanium tin. 3 . The method of claim 1 , wherein the second semiconductor material is silicon. 4 . The method of claim 1 , wherein the environment is a first compartment of a chamber. 5 . The method of claim 4 , wherein the epitaxially growing of the cap layer is performed in a second compartment of the chamber. 6 . The method of claim 1 , wherein the substrate is subjected to be processed neither at temperatures greater than 200° C. nor under pressures greater than 50 Torr. 7 . A method comprising: forming a semiconductor material over a semiconductor substrate; performing a hydrogen radical treatment process to the semiconductor material; forming a capping layer over the treated semiconductor material; and forming a gate electrode over the capping layer. 8 . The method of claim 7 , wherein forming the semiconductor material over a semiconductor substrate includes forming a recess in the semiconductor substrate and forming the semiconductor material in the recess. 9 . The method of claim 7 , forming the semiconductor material over the semiconductor substrate includes: forming a first semiconductor material layer over the semiconductor substrate; forming a second semiconductor material layer over the first semiconductor material layer; and forming a third semiconductor material layer over the second semiconductor material layer. 10 . The method of claim 9 , wherein the first semiconductor material layer is different than the second semiconductor material layer and the second semiconductor material layer is different than the third semiconductor material layer. 11 . The method of claim 7 , wherein the capping layer is formed of another semiconductor material. 12 . The method of claim 7 , wherein performing the hydrogen radical treatment process to the semiconductor material results in a passivation layer being formed over the semiconductor material. 13 . The method of claim 12 , wherein forming the capping layer over the treated semiconductor material includes forming the capping layer over the passivation layer. 14 . The method of claim 7 , wherein forming the gate electrode over the capping layer includes forming the gate electrode along a sidewall surface and a top surface of the capping layer. 15 . A method, comprising: placing a semiconductor structure in a chamber having a remote plasma source coupled thereto; generating a hydrogen plasma in the remote plasma source, the hydrogen plasma comprising hydrogen radicals; exposing a surface of the semiconductor structure to the hydrogen plasma; and epitaxially growing a cap layer on the exposed surface of the semiconductor structure. 16 . The method of claim 7 , wherein the surface of the semiconductor structure is formed of a first semiconductor material, and the cap layer is formed of a second semiconductor material. 17 . The method of claim 16 , wherein the first semiconductor material includes germanium-based material and the second semiconductor material includes silicon. 18 . The method of claim 15 , wherein before exposing the surface of the semiconductor structure to the hydrogen plasma, the surface of the semiconductor structure includes dangling germanium bonds. 19 . The method of claim 15 , wherein the semiconductor structure is a fin of a fin field-effect transistor (Fin FET). 20 . The method of claim 15 , wherein the semiconductor structure is subject to neither temperatures greater than 200° C. nor pressures greater than 50 Torr.
Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma · CPC title
Silicon, silicon germanium or germanium · CPC title
consisting of three or more layers · CPC title
Silicon, silicon germanium or germanium · CPC title
characterised by the preparation of substrate for selective deposition · CPC title
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