System and method of realignment of read data by SPI controller

Patent metadata

Field	Value
Publication number	US-9829913-B2
Application number	US-201514728451-A
Country	US
Kind code	B2
Filing date	Jun 2, 2015
Priority date	Jun 2, 2015
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

A Serial Peripheral Interface (SPI) controller is provided for use within a computer system. The SPI controller includes a clock that generates system clock signals that synchronize a data transfer operation, and a dynamic clock delay element that phase shifts the clock signals with a delay offset and outputs read data that was received during a read operation from an SPI slave device with the clock signals that were phase shifted.

First claim

What is claimed is:

1. A Serial Peripheral Interface (SPI) controller for use within a computer system, the SPI controller comprising:
a clock that generates system clock signals that synchronize a data transfer operation;
a dynamic clock delay element that phase shifts the clock signals with a delay offset and outputs read data that was received during a read operation from an SPI slave device with the clock signals that were phase shifted; and
a calibration controller that calibrates the SPI controller by determining a delay associated with the slave device when the slave device transmits a known pattern of read data to the SPI controller, wherein the calibration controller assigns the delay offset for the slave device based on the delay determined.

2. The SPI controller according to claim 1 , wherein the delay is tuned based on a condition.

3. The SPI controller according to claim 1 , wherein the dynamic clock delay element receives read data from a plurality of SPI slave devices during a plurality of read operations, and the condition associated with reading is an identification of the slave device from which the read data is received during the read operation.

4. The SPI controller according to claim 1 , wherein the condition is an environmental condition.

5. The SPI controller according to claim 1 , further comprising a calibration controller that measures a delay associated with reading data from the slave device and determines the phase offset for the slave device based on the delay measured.

6. The SPI controller according to claim 1 , wherein the SPI controller is coupled to a plurality of SPI slave devices, the SPI controller further comprising a data structure that stores an index identifying the respective SPI slave devices and a delay offset associated with each index that is configured for the associated SPI slave device.

7. The SPI controller according to claim 1 , wherein the calibration controller calibrates the SPI controller while the SPI controller and slave SPI devices are communicating by exchanging data transmission.

8. A method for reading data utilizing a Serial Peripheral Interface (SPI) management system, the method comprising:
generating system clock signals that synchronize a data transfer operation;

phase shifting the clock signals with a delay offset; and
outputting read data that was received during a read operation from an SPI slave device with the clock signals that were phase shifted; and
determining a delay associated with the slave device when the slave device transmits a known pattern of read data to the SPI controller; and

assigning the delay offset for the slave device based on the delay determined.

9. The method of claim 8 , comprising tuning the delay based on a condition.

10. The method of claim 8 , further comprising receiving read data from a plurality of SPI slave devices during a plurality of read operations, wherein the condition associated with reading is an identification of the slave device from which the read data is received during the read operation.

11. The method of claim 8 , wherein the condition is an environmental condition.

12. The method of claim 8 , further comprising:
measuring a delay associated with read data that was read from the slave device; and
determining the phase offset for the slave device based on the delay measured.

13. The method according to claim 8 , further comprising:
coupling the SM controller to a plurality of SPI slave devices;
storing indexes that identify the respective SPI slave devices; and
storing a delay offset associated with each index, the delay offset being configured for the associated SPI slave device.

14. The SPI controller according to claim 1 , wherein the delay offset is based on an inherent delay of transmission of the read data.

15. The method of claim 8 , wherein the delay offset is based on an inherent delay of transmission of the read data.

Assignees

• Goodrich Corp

Inventors

• Ramsey Scott W
• Jarok Jonathan C

Classifications

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/4291 Primary

  using a clocked protocol · CPC title

• G06F1/12 Primary

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title