Method and apparatus for source-synchronous signaling

Patent metadata

Field	Value
Publication number	US-9748960-B2
Application number	US-201414456716-A
Country	US
Kind code	B2
Filing date	Aug 11, 2014
Priority date	Mar 26, 2012
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

First claim

What is claimed is:

1. A method for operating an integrated circuit device, comprising:
phase-aligning a first data signal and a first timing signal to produce a second data signal:
generating a second timing signal from the first timing signal using a frequency multiplying circuit the second timing signal being mesochronous with respect to the first timing signal;
retiming the second data signal to produce a third data signal that is phase-aligned to a clock domain based on the second timing signal;
determining whether a first phase-relationship between the second data signal and the clock domain based on the second timing signal is within an unsafe region for retiming the second data signal based on the second timing signal;
when the first phase-relationship between the second data signal and the clock domain based on the second timing signal is within the unsafe region for retiming the second data signal based on the second timing signal, retiming the second data signal based on the first timing signal to produce a fourth data signal that has a second phase-relationship that is within a safe region for retiming the fourth data signal based on the second timing signal, and
retiming the fourth data signal based on the second timing signal to produce the third data signal; and,
when the first phase-relationship between the second data signal and the clock domain based on the second timing signal is within the safe region for retiming the data signal based on the second timing signal, retiming the second data signal based on the second timing signal to produce the third data signal.

2. The method of claim 1 , wherein determining whether the first phase-relationship between the second data signal and the clock domain based on the second timing signal is within the unsafe region for retiming the second data signal based on the second timing signal comprises:
determining whether a sampling edge of a derived timing signal is located within a predetermined phase distance from a sampling edge of the first timing signal, the derived timing signal being from the clock domain based on the second timing signal.

3. The method of claim 2 , wherein the sampling edge of the first timing signal is used to generate a data transition in the second data signal.

4. The method of claim 2 , wherein determining whether the sampling edge of the derived timing signal is located within the predetermined phase distance from the sampling edge of the first timing signal involves:
delaying the sampling edge of the derived timing signal by the predetermined phase distance;
sampling the first timing signal using the delayed sampling edge of the derived timing signal;
if the sampling output equals a first logic value, determining that the sampling edge of the derived timing signal is located within the predetermined phase distance; and
if the sampling output equals a second logic value, determining that the sampling edge of the derived timing signal is located outside of the predetermined phase distance.

5. The method of claim 1 , wherein retiming the second data signal based on the first timing signal to produce the fourth data signal comprises:
delaying the second data signal relative to the first timing signal by one half of a cycle of the first timing signal.

6. The method of claim 1 , wherein the frequency multiplying circuit includes a multiplying injection locked oscillator (MILO), wherein the first timing signal is the input to the MILO and the second timing signal is the output of the MILO.

7. An integrated circuit device comprising:
circuitry to phase-align a first data signal to a first timing signal to produce a second data signal;
frequency multiplying circuitry to generate a second timing signal from the first timing signal, the second timing signal to be mesochronous with respect to the first timing signal;
retiming circuitry to retime the second data signal to produce a third data signal that is phase-aligned to a clock domain based on the second timing signal; and
a logic circuit to determine whether a phase-relationship between the second data signal and the clock domain based on the second timing signal is within an unsafe range for retiming the second data signal based on the second timing signal, the logic circuit determining whether the phase-relationship is within the unsafe range by determining whether a sampling edge of the second timing signal is located within a predetermined phase distance to a sampling edge of the first timing signal, wherein the sampling edge of the first timing signal is used to generate a data transition in the second data signal.

8. The integrated circuit device of claim 7 , wherein the logic circuit comprises:
a delay circuit to delay the sampling edge of the second timing signal by the predetermined phase distance; and
a sampling circuit to sample the first timing signal using the delayed sampling edge of the second timing signal, the sampling circuit outputting a first logic value when the sampling edge of the second timing signal is located within the predetermined phase distance, the sampling circuit outputting a second logic value when the sampling edge of the second timing signal is located outside of the predetermined phase distance.

9. The integrated circuit device of claim 8 , wherein the retiming circuitry further comprises:
a first data path which propagates the second data signal;
a second data path which includes a phase adjusting circuit, the phase adjusting circuit to adjust the phase of the second data signal to generate a fourth data signal;
a selecting circuit which receives the second data signal and the fourth data signal as data inputs and also receives the output of the sampling circuit as a control input, wherein the selecting circuit outputs the second data signal when the control input is the second logic value and outputs the fourth data signal when the control input is first logic value; and
a retiming circuit coupled to the output of the selecting circuit, wherein the retiming circuit retimes the output of the selecting circuit based on the second timing signal.

10. The integrated circuit device of claim 9 , wherein the phase adjusting circuit generates the fourth data signal by delaying the second data signal relative to the first timing signal by one half of a cycle of the first timing signal.

11. The integrated circuit device of claim 7 , wherein the frequency multiplying circuit includes a multiplying injection locked oscillator (MILO), wherein the first timing signal is the input to the MILO and the second timing signal is the output of the MILO.

12. An integrated circuit device comprising:
a circuit to phase-align a first data signal and a first timing signal to produce a second data signal;
a frequency multiplying circuit to generate a second timing signal from the first timing signal, the second timing signal being mesochronous with respect to the first timing signal;
a clock buffer for coupling a timing reference of a source-synchronous signaling system to a second integrated circuit device, the timing reference based on the second timing signal;
retiming circuitry to retime the second data signal to produce a third data signal that is phase-aligned to a clock domain based on the second timing signal;
a data buffer for coupling a serial data signal based on the third data signal from the clock domain based on the second timing signal to the second integrated circuit device; and,
a logic circuit to determine whether a phase-relationship between the second data signal and the clock domain based on the second timing signal is within an unsafe range for retiming the second data signal based on the

Assignees

• Rambus Inc

Inventors

• Zerbe Jared L
• Leibowitz Brian S
• Su Hsuan-Jung
• Eble Iii John Cronan
• Daly Barry William
• Luo Lei
• Stone Teva J
• Wilson John
• Ren Jihong
• Dettloff Wayne D

Classifications

• H03K5/1565

  the output pulses having a constant duty cycle · CPC title

• G11C7/1066 Primary

  Output synchronization · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C7/1093

  Input synchronization · CPC title

• H04L7/0008

  Synchronisation information channels, e.g. clock distribution lines · CPC title