Techniques for reducing skew between clock signals

Patent metadata

Field	Value
Publication number	US-9660653-B1
Application number	US-201615222038-A
Country	US
Kind code	B1
Filing date	Jul 28, 2016
Priority date	Nov 28, 2014
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

A skew reduction circuit includes a first delay circuit that delays a first clock signal to generate a second clock signal and a second delay circuit that delays a third clock signal to generate a fourth clock signal. The skew reduction circuit also includes a time-to-digital converter circuit that measures a skew between the second and fourth clock signals to generate a measurement of the skew between the second and fourth clock signals. The skew reduction circuit adjusts a delay of one of the first or second delay circuits to reduce the skew between the second and fourth clock signals based on the measurement of the skew.

First claim

What is claimed is:

1. A skew reduction circuit comprising:
a first delay circuit that delays a first clock signal to generate a second clock signal;
a second delay circuit that delays a third clock signal to generate a fourth clock signal; and
a time-to-digital converter circuit that measures a skew between the second and fourth clock signals to generate a measurement of the skew between the second and fourth clock signals,
wherein the skew reduction circuit adjusts a delay of one of the first or second delay circuits to reduce the skew between the second and fourth clock signals based on the measurement of the skew.

2. The skew reduction circuit of claim 1 , wherein the time-to-digital converter circuit generates the measurement of the skew between the second and fourth clock signals in response to an indication generated by a phase detector that the second and fourth clock signals are aligned in phase within an error margin.

3. The skew reduction circuit of claim 1 , wherein the time-to-digital converter circuit comprises:
a coarse skew time-to-digital converter circuit that measures a coarse skew between the second and fourth clock signals; and
a fine skew time-to-digital converter circuit that measures a fine skew between the second and fourth clock signals.

4. The skew reduction circuit of claim 1 further comprising:
a detector circuit that generates a directional signal indicating whether a phase of the second clock signal is leading or lagging a phase of the fourth clock signal.

5. The skew reduction circuit of claim 4 , wherein the first delay circuit comprises:
a first delay line to provide a coarse delay to the second clock signal in response to a coarse skew measured between the second and fourth clock signals if the directional signal indicates that the phase of the second clock signal is leading the phase of the fourth clock signal; and
a second delay line to provide a fine delay to the second clock signal in response to a fine skew measured between the second and fourth clock signals if the directional signal indicates that the phase of the second clock signal is leading the phase of the fourth clock signal, wherein the coarse delay is larger than the fine delay.

6. The skew reduction circuit of claim 5 , wherein the second delay circuit comprises:
a third delay line to provide the coarse delay to the fourth clock signal in response to the coarse skew measured between the second and fourth clock signals if the directional signal indicates that the phase of the fourth clock signal is leading the phase of the second clock signal; and
a fourth delay line to provide the fine delay to the fourth clock signal in response to the fine skew measured between the second and fourth clock signals if the directional signal indicates that the phase of the fourth clock signal is leading the phase of the second clock signal.

7. The skew reduction circuit of claim 1 , wherein the time-to-digital converter circuit comprises third delay circuits coupled as a delay line, flip-flop circuits, and a shadow registers circuit, wherein an input of each of the flip-flop circuits is coupled to one of the third delay circuits, and wherein an output of each of the flip-flop circuits is coupled to the shadow registers circuit.

8. The skew reduction circuit of claim 1 further comprising:
a controller circuit that controls a measurement of a coarse skew between the second and fourth clock signals and that controls a measurement of a fine skew between the second and fourth clock signals, and wherein the skew reduction circuit reduces the coarse and fine skews measured between the second and fourth clock signals.

9. The skew reduction circuit of claim 1 further comprising:
a lock detector circuit that generates a lock signal to indicate when the second and fourth clock signals are aligned in phase within a static phase offset, and wherein the skew reduction circuit reduces the skew between the second and fourth clock signals in response to the lock signal.

10. A skew reduction circuit comprising:
a first delay circuit that delays a first clock signal to generate a second clock signal;
a second delay circuit that delays a third clock signal to generate a fourth clock signal;
a detector circuit that generates a directional signal indicating whether a phase of the second clock signal is leading or lagging a phase of the fourth clock signal,
wherein the skew reduction circuit determines whether to adjust a delay that the first delay circuit provides to the second clock signal or to adjust a delay that the second delay circuit provides to the fourth clock signal to reduce a skew between the second and fourth clock signals based on the directional signal; and
a time-to-digital converter circuit that measures the skew between the second and fourth clock signals.

11. The skew reduction circuit of claim 10 ,
wherein the skew reduction circuit adjusts a delay of one of the first or second delay circuits to reduce the skew between the second and fourth clock signals based on the measurement of the skew generated by the time-to-digital converter circuit.

12. The skew reduction circuit of claim 10 , wherein the time-to-digital converter circuit comprises:
a coarse skew time-to-digital converter circuit that measures a coarse skew between the second and fourth clock signals; and
a fine skew time-to-digital converter circuit that measures a fine skew between the second and fourth clock signals, wherein the skew reduction circuit reduces the coarse skew and the fine skew measured between the second and fourth clock signals.

13. The skew reduction circuit of claim 10 , wherein the skew reduction circuit generates an indication of the skew between the second and fourth clock signals in response to an indication of a phase difference between the second and fourth clock signals indicating that the second and fourth clock signals are aligned in phase within an error margin, and wherein the skew reduction circuit reduces the skew between the second and fourth clock signals based on the indication of the skew between the second and fourth clock signals.

14. The skew reduction circuit of claim 10 , wherein the first delay circuit comprises a first delay line that provides a coarse delay to the second clock signal in response to an indication of a coarse skew between the second and fourth clock signals if the second clock signal is leading the fourth clock signal, and
wherein the first delay circuit further comprises a second delay line that provides a fine delay to the second clock signal in response to an indication of a fine skew between the second and fourth clock signals if the second clock signal is leading the fourth clock signal, wherein the coarse delay is larger than the fine delay.

15. The skew reduction circuit of claim 14 , wherein the second delay circuit comprises a third delay line that provides the coarse delay to the fourth clock signal in response to the indication of the coarse skew between the second and fourth clock signals if the fourth clock signal is leading the second clock signal, and
wherein the second delay circuit further comprises a fourth delay line that provides the fine delay to the fourth clock signal in response to the indication of the fine skew between the second and fourth clock signals if the fourth clock signal is leading the second clock signal.

16. A skew reduction circuit comprising:
a first delay circuit that delays a first clock signal to generate a second clock signal;
a second delay circuit that delays a third clock signal to generate a fourth clock signal;
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Assignees

• Altera Corp

Inventors

• Khor Chuan Thim

Classifications

• H03L7/095

  using a lock detector (H03L7/087 takes precedence) · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H03L1/00 Primary

  Stabilisation of generator output against variations of physical values, e.g. power supply · CPC title

• H03L7/0891

  the up-down pulses controlling source and sink current generators, e.g. a charge pump · CPC title

• H03L7/0818 Primary

  the controlled phase shifter comprising coarse and fine delay or phase-shifting means · CPC title