Photodiode structures

Patent metadata

Field	Value
Publication number	US-10964840-B2
Application number	US-201916552664-A
Country	US
Kind code	B2
Filing date	Aug 27, 2019
Priority date	Sep 11, 2014
Publication date	Mar 30, 2021
Grant date	Mar 30, 2021

Abstract

Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.

First claim

What is claimed:

1. A method of forming a semiconductor structure, comprising:
forming a barrier layer in direct contact with both a single crystalline Ge structure and a waveguide structure, wherein the barrier layer is a different material than a dielectric material which covers the waveguide structure, the single crystalline Ge structure, an underlying metal layer, and the barrier layer; and
forming two vias filled with metal in electrical contact with the single crystalline Ge structure, wherein the two vias are positioned such that a halfway point between the two vias is not over the waveguide structure,
wherein the single crystalline Ge structure is a photodetector that is over and contacting an upper surface of the barrier layer, and the waveguide structure is under and contacting a lower surface of the barrier layer that is opposite the upper surface of the barrier layer.

2. The method of claim 1 , further comprising forming a respective capping layer between each of the two vias and the single crystalline Ge structure.

3. The method of claim 1 , wherein the single crystalline Ge structure is adjacent to the waveguide structure.

4. The method of claim 1 , wherein the barrier layer is nitride.

5. The method of claim 1 , wherein the single crystalline Ge structure includes nucleation sites.

6. The method of claim 5 , wherein the nucleation sites include a capping layer.

7. The method of claim 6 , wherein the capping layer is NiGe, using Ni as a seed layer.

8. The method of claim 1 , further comprising forming a boundary layer in the single crystalline Ge structure.

9. The method of claim 1 , further comprising forming a nucleation site on a top surface of the single crystalline Ge structure, which is a surface opposite to that which is in direct contact with the barrier layer, the nucleation site being composed of a capping layer which is between a dual damascene metal structure and the single crystalline Ge structure.

10. The method of claim 9 , wherein the nucleation site is offset in a vertical axis from the waveguide structure.

11. The method of claim 10 , further comprising forming a boundary layer within the single crystalline Ge structure, the boundary layer being offset in the vertical axis from the waveguide structure.

12. A method of forming a semiconductor structure, comprising:
exposing portions of a layer of amorphous Ge material by forming two vias in a dielectric material;
depositing a metal seed layer in each of the two vias, wherein the deposited metal seed layer directly contacts the layer of amorphous Ge material; and
performing a low temperature annealing process at less than 420° C. that results in a heat reaction between the deposited metal seed layer and the layer of amorphous Ge material, thereby beginning a nucleation process that forms a crystalline Ge structure,
wherein the two vias are positioned such that a halfway point between the two vias is not aligned over a waveguide structure contained in the dielectric material.

13. A method of forming a semiconductor structure, comprising:
forming a waveguide structure comprising silicon;
forming a barrier layer on the waveguide structure, the barrier layer comprising nitride;
forming a layer of amorphous Ge material on the barrier layer, wherein the barrier layer prevents the layer of amorphous Ge material from contacting the waveguide structure;
exposing portions of the layer of amorphous Ge material by forming two vias in a dielectric material;
depositing a metal seed layer in each of the two vias, wherein the deposited metal seed layer directly contacts the layer of amorphous Ge material; and
performing an annealing process that results in a heat reaction between the deposited metal seed layer and the layer of amorphous Ge material, thereby beginning a nucleation process that forms a crystalline Ge structure.

14. The method of claim 13 , wherein the two vias are positioned such that a halfway point between the two vias is not over the waveguide structure.

15. The method of claim 13 wherein the barrier layer is a different material than the dielectric material.

16. The method of claim 15 , wherein the dielectric material surrounds the waveguide structure, an underlying metal layer, and the barrier layer.

17. The method of claim 13 wherein the layer of amorphous Ge material is offset with respect to the waveguide structure such that the layer of amorphous Ge material is not centered on the waveguide structure.

Assignees

• IBM

Inventors

• Ellis-Monaghan John J
• Gambino Jeffrey P
• Jaffe Mark D
• Peterson Kirk D

Classifications

• H10W44/216

  Waveguides, e.g. strip lines · CPC title

• H10F77/933

  for devices having potential barriers · CPC title

• H10F77/413

  directly associated or integrated with the devices, e.g. back reflectors (directly associated or integrated with photovoltaic cells H10F77/42) · CPC title

• H10F77/122

  comprising only Group IV materials · CPC title

• H10F71/131

  Recrystallisation; Crystallization of amorphous or microcrystalline semiconductors · CPC title