Photodiode structures

Patent metadata

Field	Value
Publication number	US-9627575-B2
Application number	US-201414483584-A
Country	US
Kind code	B2
Filing date	Sep 11, 2014
Priority date	Sep 11, 2014
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.

First claim

What is claimed:

1. A method, comprising:
forming a waveguide structure in a dielectric layer;
forming a Ge material adjacent to the waveguide structure in a back end of the line (BEOL) metal layer; and
crystallizing the Ge material into a crystalline Ge structure by an annealing process with a metal layer in contact with the Ge material, wherein:
the forming of the Ge material comprises:
depositing and patterning a barrier layer directly on the waveguide structure; and
depositing and patterning the layer of Ge material in an amorphous state directly on the barrier layer; and

the crystallizing the Ge material into the crystalline Ge structure comprises:
depositing the metal layer as a metal seed layer directly on the Ge material which has been exposed by etching a trench and via in the dielectric layer; and
laterally crystallizing the Ge material by a low temperature annealing process between 350° C. and 420° C.

2. The method claim 1 , wherein the metal layer is a metal seed layer formed in direct contact with the Ge material within a via formed to expose a surface of the Ge material, the annealing process is performed after deposition of the metal seed layer is formed in direct contact with the Ge material, within the via of the dielectric layer.

3. The method of claim 1 , wherein the metal layer is a metal seed layer of Ni in contact with the Ge material.

4. The method of claim 1 , wherein the metal layer is a germanide or a eutectic.

5. The method of claim 1 , wherein any unreacted metal layer is removed after the low temperature annealing process.

6. The method of claim 1 , wherein the metal layer is a metal seed layer deposited in a via and on a surface of the Ge material.

7. The method of claim 1 , wherein the metal layer is a metal seed layer deposited in two vias in a dielectric material composing BEOL wiring layers, offset from a center of the Ge material.

8. The method of claim 1 , wherein the metal layer is a metal seed layer deposited in one of at least two vias.

9. The method of claim 1 , wherein the Ge material is amorphous Ge prior to the low temperature annealing process.

10. The method of claim 1 , wherein the crystallizing of the Ge material comprises:
forming at least one via in a dielectric material to expose the Ge material;
forming a metal seed layer in the at least one via;
annealing the metal seed layer at a temperature of about 350° C. to 420° C. to form a capping layer on the Ge material and to laterally crystallize the Ge material; and
removing any unreacted metal seed layer.

11. The method claim 10 , further comprising filling the via with metal, in contact with the Ge material.

12. The method of claim 11 , further comprising removing the capping layer such that the metal in the via is in direct contact with the metal.

13. The method of claim 1 , wherein the barrier layer is nitride, the metal seed layer is formed on sidewalls of the trench and via that exposes a surface of the Ge material prior to the deposition of the metal seed layer, and further comprising forming a boundary layer in the crystallized Ge material, which is positioned to a side of the waveguide structure.

Assignees

• IBM

Inventors

• Ellis-Monaghan John J
• Gambino Jeffrey P
• Jaffe Mark D
• Peterson Kirk D

Classifications

• H10W44/216

  Waveguides, e.g. strip lines · CPC title

• Y02E10/50

  Photovoltaic [PV] energy · CPC title

• G02B6/12004

  Combinations of two or more optical elements · CPC title

• G02B6/12

  of the integrated circuit kind (electric integrated circuits H10B, H10D84/00 - H10D89/00, H10F19/00, H10F39/00, H10H29/00, H10K19/00, H10K39/00, H10K59/00, H10N19/00, H10N39/00, H10N59/00, H10N69/00, H10N79/00, H10N89/00) · CPC title

• H01P1/172

  using a dielectric element · CPC title