Vertically stacked nanowire field effect transistors

Patent metadata

Field	Value
Publication number	US-2017221884-A1
Application number	US-201615097142-A
Country	US
Kind code	A1
Filing date	Apr 12, 2016
Priority date	Feb 1, 2016
Publication date	Aug 3, 2017
Grant date	—

Abstract

A device includes a substrate, a first nanowire field effect transistor (FET), and a second nanowire FET positioned between the substrate and the first nanowire FET. The device also includes a first nanowire electrically coupled to the first nanowire FET and to the second nanowire FET.

First claim

1 . A device comprising:
a substrate; a first nanowire field effect transistor (FET); a second nanowire FET positioned between the substrate and the first nanowire FET; and a first nanowire electrically coupled to the first nanowire FET and to the second nanowire FET.

2 . The device of claim 1 , further comprising multiple nanowires, the multiple nanowires including the first nanowire, wherein each of the multiple nanowires extends in a direction substantially perpendicular to a surface of the substrate.

3 . The device of claim 2 , wherein each of the multiple nanowires is electrically coupled to the first nanowire FET and to the second nanowire FET.

4 . The device of claim 1 , wherein the first nanowire FET and the second nanowire FET form a first nanowire FET stack, and further comprising a second nanowire FET stack coupled to the substrate.

5 . The device of claim 4 , wherein the second nanowire FET stack includes a plurality of nanowire FETs and a second nanowire coupled to each nanowire FET of the plurality of nanowire FETs.

6 . The device of claim 4 , wherein the second nanowire FET stack includes a second nanowire electrically coupled to a plurality of nanowire FETs of the second nanowire FET stack, wherein the first nanowire includes a first material and the second nanowire includes a second material that is different from the first material.

7 . The device of claim 6 , further comprising an isolation trench between the first nanowire FET stack and the second nanowire FET stack, wherein first material includes an N-type dopant and the second material includes a P-type dopant.

8 . The device of claim 4 , wherein the first nanowire FET stack includes a first number of nanowire FETs and the second nanowire FET stack includes a second number of nanowire FETs, the second number different from the first number.

9 . The device of claim 4 , further comprising a plurality of additional nanowire FET stacks coupled to the substrate, the first nanowire FET stack, the second nanowire FET stack, and the plurality of additional nanowire FET stacks arranged in a grid.

10 . The device of claim 4 , further comprising an isolation trench between the first nanowire FET stack and the second nanowire FET stack.

11 . The device of claim 4 , further comprising a communications device, a personal digital assistant (PDA), a navigation device, a fixed location data unit, a set top box, a music player, a video player, an entertainment unit, or a computer into which the first nanowire FET stack and the second nanowire FET stack are integrated.

12 . The device of claim 1 , further comprising at least one additional nanowire FET positioned between the substrate and the second nanowire FET, the first nanowire electrically coupled to the at least one additional nanowire FET.

13 . The device of claim 1 , further comprising a common source line coupled to source regions of the first nanowire FET and the second nanowire FET.

14 . The device of claim 1 , further comprising a common drain line coupled to drain regions of the first nanowire FET and the second nanowire FET.

15 . The device of claim 1 , further comprising a common gate line coupled to gate regions of the first nanowire FET and the second nanowire FET.

16 . The device of claim 1 , wherein the first nanowire FET includes a first source region, a first drain region, and a first gate region between the first source region and the first drain region, and the second nanowire FET includes the first drain region, a second source region, and a second gate region between the first drain region and the second source region.

17 . The device of claim 1 , wherein the first nanowire FET includes a first drain region, a first source region, and a first gate region between the first drain region and the first source region, and the second nanowire FET includes the first source region, a second drain region, and a second gate region between the first source region and the second drain region.

18 . A method comprising:
forming a first nanowire field effect transistor (FET) on a substrate; and forming a second nanowire FET on the first nanowire FET to form a nanowire FET stack having a nanowire that is electrically coupled to the first nanowire FET and to the second nanowire FET.

19 . The method of claim 18 , wherein forming the first nanowire FET includes:
forming a first source region electrically coupled to the nanowire; forming a first drain region electrically coupled to the nanowire; and forming a first gate region between the first source region and the first drain region, the first gate region electrically coupled to the nanowire.

20 . The method of claim 19 , wherein forming the second nanowire FET includes:
forming a second source region electrically coupled to the nanowire; and forming a second gate region between the first drain region and the second source region, the second gate region electrically coupled to the nanowire.

21 . The method of claim 19 , wherein forming the second nanowire FET include:
forming a second drain region electrically coupled to the nanowire; and forming a second gate region between the first source region and the second drain region, the second gate region electrically coupled to the nanowire.

22 . The method of claim 18 , further comprising before forming the first nanowire FET and the second nanowire FET, forming a layer stack on the substrate, the layer stack including dummy layers separated by spacer layers.

23 . The method of claim 22 , wherein the dummy layers include gate region dummy layers, drain region dummy layers and source region dummy layers.

24 . The method of claim 23 , wherein the first nanowire FET and the second nanowire FET are formed concurrently by:
performing a first set of selective etches to form an opening in the dummy layers; depositing a first set of one or more materials in the opening to form the nanowire; performing a second set of selective etches to remove the gate region dummy layers; depositing a second set of one or more materials to form a gate region of each nanowire FET of the nanowire FET stack; performing a third set of selective etches to remove the drain region dummy layers; depositing a third set of one or more materials to form a drain region of each nanowire FET of the nanowire FET stack; performing a fourth set of selective etches to remove the source region dummy layers; and depositing a fourth set of one or more materials to form a source region of each nanowire FET of the nanowire FET stack.

25 . A non-transitory computer-readable medium comprising processor executable instructions that, when executed by a processor, cause the processor to:
initiate formation of a nanowire field effect transistor (FET) stack on a substrate by:
forming a first nanowire FET on the substrate; and
forming a second nanowire FET on the first nanowire FET such that a nanowire is electrically coupled to the first nanowire FET and to the second nanowire FET.

26 . The non-transitory computer-readable medium of claim 25 , wherein initiating formation of the nanowire FET stack on the substrate further includes forming a layer stack on the substrate, the layer stack including gate region dummy layers, drain region dummy layers and source region dummy layers.

27 . The non-transitory computer-readable medium of claim 26 , wherein initiat

Assignees

• Qualcomm Inc

Inventors

• Machkaoutsan Vladimir
• Song Stanley Seungchul
• Badaroglu Mustafa
• Zhu John Jianhong
• Bao Junjing
• Xu Jeffrey Junhao
• Yang Da
• Nowak Matthew Michael
• Yeap Choh Fei

Classifications

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title

• H01L21/823481

  Electricity · mapped topic

• H01L21/823418

  Electricity · mapped topic

• H01L29/0669

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic