Epitaxial growth techniques for reducing nanowire dimension and pitch

Patent metadata

Field	Value
Publication number	US-9449820-B2
Application number	US-201414578833-A
Country	US
Kind code	B2
Filing date	Dec 22, 2014
Priority date	Dec 22, 2014
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

Techniques for reducing nanowire dimension and pitch are provided. In one aspect, a pitch multiplication method for nanowires includes the steps of: providing an SOI wafer having an SOI layer separated from a substrate by a BOX, wherein the SOI layer includes Si; patterning at least one nanowire in the SOI layer, wherein the at least one nanowire as-patterned has a square cross-sectional shape with flat sides; growing epitaxial SiGe on the outside of the at least one nanowire using an epitaxial process selective for growth of the epitaxial SiGe on the flat sides of the at least one nanowire; removing the at least one nanowire selective to the epitaxial SiGe, wherein the epitaxial SiGe that remains includes multiple epitaxial SiGe wires having been formed in place of the at least one nanowire that has been removed.

First claim

What is claimed is:

1. A pitch multiplication method for nanowires, the method comprising the steps of:
providing a semiconductor-on-insulator (SOI) wafer having an SOI layer separated from a substrate by a buried oxide (BOX), wherein the SOI layer comprises silicon (Si);
patterning at least one nanowire in the SOI layer, wherein the at least one nanowire as-patterned has a square cross-sectional shape with flat sides;
growing epitaxial silicon germanium (SiGe) on an outside of the at least one nanowire using an epitaxial process that selectively grows the epitaxial SiGe on the flat sides of the at least one nanowire, wherein by way of the growing step the at least one nanowire is encapsulated in the epitaxial SiGe;
etching back the epitaxial SiGe to expose the at least one nanowire; and
removing the at least one nanowire selective to the epitaxial SiGe, wherein the epitaxial SiGe that remains comprises multiple epitaxial SiGe wires having been formed in place of the at least one nanowire that has been removed.

2. The pitch multiplication method of claim 1 , wherein the epitaxial SiGe is etched back using an isotropic etching process selective for etching SiGe.

3. The pitch multiplication method of claim 1 , wherein the at least one nanowire is removed selective to the epitaxial SiGe using a wet etching process.

4. The pitch multiplication method of claim 1 , further comprising the step of:
reshaping the multiple epitaxial SiGe wires to give the multiple epitaxial SiGe wires a round cross-sectional shape.

5. The pitch multiplication method of claim 4 , further comprising the step of:
increasing a diameter of the multiple epitaxial SiGe wires using an epitaxial growth process.

6. The pitch multiplication method of claim 1 , wherein the step of patterning the at least one nanowire in the SOI layer comprises:
patterning pads in the SOI layer, wherein the at least one nanowire connects the pads to form a ladder-like structure.

7. The pitch multiplication method of claim 6 , further comprising the step of:
growing the epitaxial SiGe on the pads.

8. The pitch multiplication method of claim 1 , wherein the at least one nanowire has four flat sides and wherein four of the multiple epitaxial SiGe wires are formed.

Assignees

• IBM

Inventors

• Cohen Guy M
• Guillorn Michael A
• Lauer Isaac
• Sleight Jeffrey W

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/2926

  Crystal orientations · CPC title

• H10P14/2925

  Surface structures · CPC title

• H10P14/2924

  Structures · CPC title