DBI to Si bonding for simplified handle wafer

Patent metadata

Field	Value
Publication number	US-10964664-B2
Application number	US-201916386261-A
Country	US
Kind code	B2
Filing date	Apr 17, 2019
Priority date	Apr 20, 2018
Publication date	Mar 30, 2021
Grant date	Mar 30, 2021

Abstract

Devices and techniques include process steps for preparing various microelectronic components for bonding, such as for direct bonding without adhesive. The processes include providing a first bonding surface on a first surface of the microelectronic components, bonding a handle to the prepared first bonding surface, and processing a second surface of the microelectronic components while the microelectronic components are gripped at the handle. In some embodiments, the processes include removing the handle from the first bonding surface, and directly bonding the microelectronic components at the first bonding surface to other microelectronic components.

First claim

What is claimed is:

1. A method of forming a microelectronic assembly, comprising:
preparing a first bonding surface of a first substrate, including planarizing the first bonding surface to have a first predetermined maximum surface variance, the first bonding surface comprising a dielectric and including one or more conductive interconnects;
direct bonding a sacrificial second substrate to the first bonding surface using a direct dielectric-to-dielectric, non-adhesive technique, the second substrate comprising a handle to support the first substrate during processing of the first substrate;
while supporting the first substrate at the handle, the handle bonded to the first bonding surface of the first substrate, planarizing a second surface of the first substrate, opposite the first surface, to form a second bonding surface of the first substrate having a second predetermined maximum surface variance;
singulating the first substrate into a plurality of microelectronic dies; and
removing the handle.

2. The method of forming a microelectronic assembly of claim 1 , further comprising planarizing a bonding surface of the second substrate and preparing the bonding surface of the second substrate with an etch comprising sulfuric acid and hydrogen peroxide prior to bonding the bonding surface of the second substrate to the first bonding surface of the first substrate.

3. The method of forming a microelectronic assembly of claim 1 , further comprising planarizing a bonding surface of the second substrate and forming a thin oxide layer via a thermal oxidation process on the bonding surface of the second substrate prior to bonding the bonding surface of the second substrate to the first bonding surface of the first substrate.

4. The method of forming a microelectronic assembly of claim 1 , further comprising thinning the first substrate while the first substrate is bonded to the handle and prior to forming the second bonding surface.

5. The method of forming a microelectronic assembly of claim 4 , wherein the first substrate is thinned to have a thickness of less than 20 microns and a total thickness variation (TTV) of less than 3 microns.

6. The method of forming a microelectronic assembly of claim 1 , further comprising depositing an insulating layer at the second surface to form the second bonding surface.

7. The method of forming a microelectronic assembly of claim 1 , wherein the handle is removed via selective wet etching, selective dry etching, chemical mechanical planarization, back grinding, or a combination of selective wet etching, selective dry etching, chemical mechanical planarization and back grinding.

8. The method of forming a microelectronic assembly of claim 1 , further comprising plasma activating the first bonding surface of the first substrate.

9. The method of forming a microelectronic assembly of claim 1 , further comprising heat annealing the first and second substrates after bonding the second substrate to the first substrate.

10. The method of forming a microelectronic assembly of claim 1 , wherein the handle is removed prior to singulating the first substrate via back grinding, etching, and chemical mechanical planarization.

11. The method of forming a microelectronic assembly of claim 1 , further comprising depositing a protective coating on the first bonding surface of the first substrate prior to singulating the first substrate into a plurality of microelectronic dies.

12. The method of forming a microelectronic assembly of claim 1 , further comprising stacking and bonding the microelectronic dies to a prepared host die, wafer, or substrate using a direct bonding technique without adhesive, while the first substrate is bonded to the handle.

13. The method of forming a microelectronic assembly of claim 1 , further comprising:
temporarily bonding a carrier to the second bonding surface of the first substrate; and
wherein the handle is removed while the first substrate is supported at the carrier.

14. The method of forming a microelectronic assembly of claim 1 , wherein the second substrate comprises an oxide.

15. The method of forming a microelectronic assembly of claim 1 , wherein the second substrate comprises silicon, and wherein the handle is removed via a selective etchant.

16. The method of forming a microelectronic assembly of claim 1 , wherein the second substrate comprises silicon, and wherein the first bonding surface is ready for further bonding after removal of the silicon without further CMP of the first bonding surface.

17. A method of forming a microelectronic assembly, comprising:
preparing a first bonding surface of a first substrate, including planarizing the first bonding surface to have a first predetermined maximum surface variance, the first bonding surface comprising a dielectric and including one or more conductive interconnects;
direct bonding a sacrificial second substrate to the first bonding surface using a direct dielectric-to-dielectric, non-adhesive technique to utilize the second substrate as a handle; and
while supporting the first substrate at the handle, the handle bonded to the first bonding surface of the first substrate, planarizing a second surface of the first substrate, opposite the first surface, to form a second bonding surface of the first substrate having a second predetermined maximum surface variance; and
singulating the first substrate into a plurality of microelectronic dies.

Assignees

• Invensas Bonding Tech Inc

Inventors

• Mandalapu Chandrasekhar
• Fountain Jr Gaius Gillman
• Gao Guilian

Classifications

• H10W72/921

  Structures or relative sizes of bond pads · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title